公开(公告)号：US08700837B1

公开(公告)日：2014-04-15

申请号：US13367246

申请日：2012-02-06

申请人： Hare Krishna Verma ,  Manoj Gunwani ,  Ravi Sunkavalli

发明人： Hare Krishna Verma ,  Manoj Gunwani ,  Ravi Sunkavalli

IPC分类号： G06F13/00 ,  G06F7/38

CPC分类号： G06F7/483 ,  G06F7/5443

摘要： A high performance field programmable gate array is described with one or more signal processing engines coupled to a programmable logic fabric. Each signal processing engine includes a signal processing unit for performing specifying tasks and a bus-based configurable connection box for routing a bus-based input to a bus-based output. The signal processing unit has a floating point unit (FPU)/multiply accumulate (MAC) for computation and register files for storing information. The programmable logic fabric is coupled to the one or more signal processing engines for routing of information between the signal processing engines.

摘要翻译： 使用耦合到可编程逻辑结构的一个或多个信号处理引擎来描述高性能现场可编程门阵列。 每个信号处理引擎包括用于执行指定任务的信号处理单元和用于将基于总线的输入路由到基于总线的输出的基于总线的可配置连接盒。 信号处理单元具有用于计算的浮点单元（FPU）/乘法累加（MAC）和用于存储信息的寄存器文件。 可编程逻辑结构耦合到一个或多个信号处理引擎，用于在信号处理引擎之间路由信息。

公开(公告)号：US08131909B1

公开(公告)日：2012-03-06

申请号：US11857858

申请日：2007-09-19

申请人： Hare Krishna Verma ,  Manoj Gunwani ,  Ravi Sunkavalli

发明人： Hare Krishna Verma ,  Manoj Gunwani ,  Ravi Sunkavalli

IPC分类号： G06F13/00 ,  G06F7/38

CPC分类号： G06F7/483 ,  G06F7/5443

摘要： A high performance field programmable gate array is described with one or more signal processing engines coupled to a programmable logic fabric. Each signal processing engine includes a signal processing unit for performing specifying tasks and a bus-based configurable connection box for routing a bus-based input to a bus-based output. The signal processing unit has a floating point unit (FPU)/multiply accumulate (MAC) for computation and register files for storing information. The programmable logic fabric is coupled to the one or more signal processing engines for routing of information between the signal processing engines.

摘要翻译： 使用耦合到可编程逻辑结构的一个或多个信号处理引擎来描述高性能现场可编程门阵列。 每个信号处理引擎包括用于执行指定任务的信号处理单元和用于将基于总线的输入路由到基于总线的输出的基于总线的可配置连接盒。 信号处理单元具有用于计算的浮点单元（FPU）/乘法累加（MAC）和用于存储信息的寄存器文件。 可编程逻辑结构耦合到一个或多个信号处理引擎，用于在信号处理引擎之间路由信息。

公开(公告)号：US07970979B1

公开(公告)日：2011-06-28

申请号：US11857661

申请日：2007-09-19

申请人： Hare Krishna Verma ,  Manoj Gunwani ,  Ravi Sunkavalli

发明人： Hare Krishna Verma ,  Manoj Gunwani ,  Ravi Sunkavalli

IPC分类号： G06F13/00 ,  G06F13/12 ,  G06F13/38 ,  G06F13/40 ,  G06F7/38 ,  H03K19/173 ,  H03K19/177

CPC分类号： G06F7/483 ,  G06F7/5443 ,  H03K19/17736

摘要： A high performance field programmable gate array is described with one or more signal processing engines coupled to a programmable logic fabric. Each signal processing engine includes a signal processing unit for performing specifying tasks and a bus-based configurable connection box for routing a bus-based input to a bus-based output. The signal processing unit has a floating point unit (FPU)/multiply accumulate (MAC) for computation and register files for storing information. The programmable logic fabric is coupled to the one or more signal processing engines for routing of information between the signal processing engines.

摘要翻译： 使用耦合到可编程逻辑结构的一个或多个信号处理引擎来描述高性能现场可编程门阵列。 每个信号处理引擎包括用于执行指定任务的信号处理单元和用于将基于总线的输入路由到基于总线的输出的基于总线的可配置连接盒。 信号处理单元具有用于计算的浮点单元（FPU）/乘法累加（MAC）和用于存储信息的寄存器文件。 可编程逻辑结构耦合到一个或多个信号处理引擎，用于在信号处理引擎之间路由信息。

公开(公告)号：US07428722B2

公开(公告)日：2008-09-23

申请号：US12007705

申请日：2008-01-15

申请人： Ravi Sunkavalli ,  Hare Krishna Verma ,  Sudip Nag ,  Elliott Delaye

发明人： Ravi Sunkavalli ,  Hare Krishna Verma ,  Sudip Nag ,  Elliott Delaye

IPC分类号： H03K19/00

CPC分类号： H03K19/1737

摘要： Logic design apparatus and method provides serial multiplexer chains in a programmable logic fabric, each element in the chain either selects output of block, or passes output from earlier element of the chain. Select line is a decoder structure or output from configurable function generator that is configured at power-on to create correct selection. Using such structure, larger multiplexer, including priority multiplexers, tristate buses or larger look-up tables (LUTs) can be created. These novel structures can implement priority, non-priority or tristate multiplexers.

公开(公告)号：US20080129334A1

公开(公告)日：2008-06-05

申请号：US12007705

申请日：2008-01-15

申请人： Ravi Sunkavalli ,  Hare Krishna Verma ,  Sudip Nag ,  Elliott Delaye

发明人： Ravi Sunkavalli ,  Hare Krishna Verma ,  Sudip Nag ,  Elliott Delaye

IPC分类号： H03K19/00 ,  G06F17/50

CPC分类号： H03K19/1737

摘要： Logic design apparatus and method provides serial multiplexer chains in a programmable logic fabric, each element in the chain either selects output of block, or passes output from earlier element of the chain. Select line is a decoder structure or output from configurable function generator that is configured at power-on to create correct selection. Using such structure, larger multiplexer, including priority multiplexers, tristate buses or larger look-up tables (LUTs) can be created. These novel structures can implement priority, non-priority or tristate multiplexers.

公开(公告)号：US07358761B1

公开(公告)日：2008-04-15

申请号：US11040633

申请日：2005-01-21

申请人： Ravi Sunkavalli ,  Hare Krishna Verma ,  Sudip Nag ,  Elliott Delaye

发明人： Ravi Sunkavalli ,  Hare Krishna Verma ,  Sudip Nag ,  Elliott Delaye

IPC分类号： H03K19/173

CPC分类号： H03K19/1737

摘要： Logic design apparatus and method provides serial multiplexer chains in a programmable logic fabric, each element in the chain either selects output of block, or passes output from earlier element of the chain. Select line is a decoder structure or output from configurable function generator that is configured at power-on to create correct selection. Using such structure, larger multiplexer, including priority multiplexers, tristate buses or larger look-up tables (LUTs) can be created. These novel structures can implement priority, non-priority or tristate multiplexers.

摘要翻译： 逻辑设计装置和方法提供可编程逻辑结构中的串行复用器链，链中的每个元件选择块的输出，或者从链的早期元素传递输出。 选择行是可配置函数发生器的解码器结构或输出，在上电时配置，以创建正确的选择。 使用这种结构，可以创建更大的多路复用器，包括优先复用器，三态总线或更大的查找表（LUT）。 这些新颖的结构可以实现优先级，非优先级或三态多路复用器。

公开(公告)号：US07358765B2

公开(公告)日：2008-04-15

申请号：US11066336

申请日：2005-02-23

申请人： Hare K. Verma ,  Ravi Sunkavalli ,  Manoj Gunwani ,  Elliott Delaye

发明人： Hare K. Verma ,  Ravi Sunkavalli ,  Manoj Gunwani ,  Elliott Delaye

IPC分类号： H03K19/177

CPC分类号： H03K19/17728

摘要： A dedicated logic cell in a programmable logic structure is described that comprises the following primary components: a configurable logic function or look-up table (LL), a dedicated logic function (DL), a sequential logic function (LS), and a control logic function (LC). In this illustration, the dedicated logic cell comprises two configurable logic functions, two sequential logic functions, a dedicate logic function, and a control logic function. In a first embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-input function, an AND function, an OR function, or an XOR function. In a second embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-to-1 multiplexer function. In a third embodiment, the dedicated logic cell is constructed with a plurality of configurable logic functions that operate as a two 6-input function with separate inputs. In a fourth embodiment, the dedicated logic cell is constructed with a combination of a configurable logic function with sequential logic functions that operate as a loadable, resettable, clearable shift register. In a fifth embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions, a dedicated logic function, and sequential logic functions that operate as an accumulator.

摘要翻译： 描述了可编程逻辑结构中的专用逻辑单元，其包括以下主要组件：可配置逻辑功能或查找表（LL），专用逻辑功能（DL），顺序逻辑功能（LS）和控制 逻辑功能（LC）。 在该图示中，专用逻辑单元包括两个可配置逻辑功能，两个顺序逻辑功能，专用逻辑功能和控制逻辑功能。 在第一实施例中，专用逻辑单元由可配置的逻辑功能的组合构成，该组合逻辑功能耦合到专用逻辑功能，以执行四个2输入功能，“与”功能，“或”功能或“异或”功能。 在第二实施例中，专用逻辑单元由可配置逻辑功能的组合构成，该逻辑单元耦合到专用逻辑功能，以便执行四个2对1多路复用器功能。 在第三实施例中，专用逻辑单元由多个可配置的逻辑功能构成，其作为具有单独输入的两个6输入功能。 在第四实施例中，专用逻辑单元由可配置逻辑功能和顺序逻辑功能的组合构成，其作为可装载的，可重置的，可清除的移位寄存器来操作。 在第五实施例中，专用逻辑单元由可配置逻辑功能，专用逻辑功能和作为累加器操作的顺序逻辑功能的组合构成。

公开(公告)号：US07814136B1

公开(公告)日：2010-10-12

申请号：US11344694

申请日：2006-02-01

申请人： Hare K. Verma ,  Ravi Sunkavalli ,  Manoj Gunwani

发明人： Hare K. Verma ,  Ravi Sunkavalli ,  Manoj Gunwani

IPC分类号： G06F7/38

CPC分类号： G06F7/483 ,  G06F7/5443 ,  G06F7/57 ,  H03K19/17736

摘要： A programmable system is disclosed having multiple configurable floating point units (“FPU”) that are coupled to multiple programmable logic and routing blocks and multiple memories. Each floating point unit has static configuration blocks and dynamic configuration blocks, where the dynamic configuration blocks can be reconfigured to perform a different floating point unit function. A floating point unit includes a pre-normalization for shifting an exponent calculation as well as shifting and aligning a mantissa, and a post-normalization for normalizing and rounding a received input. The post-normalization receives an input Z and realigns the input, normalizes the input and rounds the input Z.

摘要翻译： 公开了一种可编程系统，其具有耦合到多个可编程逻辑和路由块和多个存储器的多个可配置浮点单元（“FPU”）。 每个浮点单元具有静态配置块和动态配置块，其中动态配置块可以被重新配置以执行不同的浮点单元功能。 浮点单元包括用于移位指数计算以及移位和对准尾数的预归一化，以及用于归一化和舍入所接收的输入的后归一化。 后归一化接收输入Z并重新对准输入，对输入进行归一化并舍入输入Z。

公开(公告)号：US20070075739A1

公开(公告)日：2007-04-05

申请号：US11539777

申请日：2006-10-09

申请人： Hare Verma ,  Ravi Sunkavalli ,  Manoj Gunwani ,  Elliott Delaye

发明人： Hare Verma ,  Ravi Sunkavalli ,  Manoj Gunwani ,  Elliott Delaye

IPC分类号： H03K19/177

CPC分类号： H03K19/17728

摘要： A dedicated logic cell in a programmable logic structure is described that comprises the following primary components: a configurable logic function or look-up table (LL), a dedicated logic function (DL), a sequential logic function (LS), and a control logic function (LC). In this illustration, the dedicated logic cell comprises two configurable logic functions, two sequential logic functions, a dedicate logic function, and a control logic function. In a first embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-input function, an AND function, an OR function, or an XOR function. In a second embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-to-1 multiplexer function. In a third embodiment, the dedicated logic cell is constructed with a plurality of configurable logic functions that operate as a two 6-input function with separate inputs. In a fourth embodiment, the dedicated logic cell is constructed with a combination of a configurable logic function with sequential logic functions that operate as a loadable, resettable, clearable shift register. In a fifth embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions, a dedicated logic function, and sequential logic functions that operate as an accumulator.

摘要翻译： 描述了可编程逻辑结构中的专用逻辑单元，其包括以下主要组件：可配置逻辑功能或查找表（LL），专用逻辑功能（DL），顺序逻辑功能（LS）和控制 逻辑功能（LC）。 在该图示中，专用逻辑单元包括两个可配置逻辑功能，两个顺序逻辑功能，专用逻辑功能和控制逻辑功能。 在第一实施例中，专用逻辑单元由可配置的逻辑功能的组合构成，该组合逻辑功能耦合到专用逻辑功能，以执行四个2输入功能，“与”功能，“或”功能或“异或”功能。 在第二实施例中，专用逻辑单元由可配置逻辑功能的组合构成，该逻辑单元耦合到专用逻辑功能，以便执行四个2对1多路复用器功能。 在第三实施例中，专用逻辑单元由多个可配置的逻辑功能构成，其作为具有单独输入的两个6输入功能。 在第四实施例中，专用逻辑单元由可配置逻辑功能和顺序逻辑功能的组合构成，其作为可装载的，可重置的，可清除的移位寄存器来操作。 在第五实施例中，专用逻辑单元由可配置逻辑功能，专用逻辑功能和作为累加器操作的顺序逻辑功能的组合构成。

公开(公告)号：US08429214B2

公开(公告)日：2013-04-23

申请号：US12885103

申请日：2010-09-17

申请人： Hare K. Verma ,  Ravi Sunkavalli ,  Manoj Gunwani

发明人： Hare K. Verma ,  Ravi Sunkavalli ,  Manoj Gunwani

IPC分类号： G06F7/38

CPC分类号： G06F7/483 ,  G06F7/5443 ,  G06F7/57 ,  H03K19/17736

摘要： A programmable system is disclosed having multiple configurable floating point units (“FPU”) that are coupled to multiple programmable logic and routing blocks and multiple memories. Each floating point unit has static configuration blocks and dynamic configuration blocks, where the dynamic configuration blocks can be reconfigured to perform a different floating point unit function. A floating point unit includes a pre-normalization for shifting an exponent calculation as well as shifting and aligning a mantissa, and a post-normalization for normalizing and rounding a received input. The post-normalization receives an input Z and realigns the input, normalizes the input and rounds the input Z.

摘要翻译： 公开了一种可编程系统，其具有耦合到多个可编程逻辑和路由块和多个存储器的多个可配置浮点单元（“FPU”）。 每个浮点单元具有静态配置块和动态配置块，其中动态配置块可以被重新配置以执行不同的浮点单元功能。 浮点单元包括用于移位指数计算以及移位和对准尾数的预归一化，以及用于归一化和舍入所接收的输入的后归一化。 后归一化接收输入Z并重新对准输入，对输入进行归一化并舍入输入Z。