公开(公告)号：US20080247449A1

公开(公告)日：2008-10-09

申请号：US12047448

申请日：2008-03-13

申请人： Hideaki WADA

发明人： Hideaki WADA

IPC分类号： H04B17/00

CPC分类号： H04L25/45

摘要： The object of the invention is to checking the timing easily and in shorter time, and reduce the power consumption without any influence on other circuits functions. The solutions are as follows. By the “1” detecting counter, the “0” detecting counter, and the data validity judging circuit in the checking circuit of transmission control included in the DSRC baseband circuit of the transmission apparatus, it becomes the possible to judge the data validity of the transmission data TX_DI—0. Additionally, by the transmission enable counter 23 and the matched transmission-start-timing judging circuit, it becomes possible to judge the transmission-start-timings of the transmission enable signal TXW_N—0 and the transmission data TX_DI—0. Furthermore, by the transmission-end-timing judging circuit, it becomes possible to judge the end timing of each slot type of the transmission data.

摘要翻译： 本发明的目的是在时间上更容易地检查时序，降低功耗而不影响其它电路的功能。 解决方案如下。 通过“1”检测计数器，发送装置的DSRC基带电路中包含的发送控制的检查电路中的“0”检测计数器和数据有效性判定电路，可以判断数据的有效性 传输数据TX_DI 0。 此外，通过发送使能计数器23和匹配的发送开始定时判断电路，可以判断发送使能信号TXW_N＆gt; 0的发送开始定时和发送数据TX_DI _{- 0。 此外，通过发送结束定时判断电路，可以判断各个时隙类型的发送数据的结束定时。}

公开(公告)号：US20070066383A1

公开(公告)日：2007-03-22

申请号：US11390417

申请日：2006-03-28

申请人： Koichi Mori ,  Nakayasu Tsukahara ,  Hideaki Wada ,  Kuniaki Honno ,  Hiroshi Irimajiri ,  Takumi Nishi ,  Hiroaki Oosera ,  Akio Fujita ,  Yusuke Kikuchi

发明人： Koichi Mori ,  Nakayasu Tsukahara ,  Hideaki Wada ,  Kuniaki Honno ,  Hiroshi Irimajiri ,  Takumi Nishi ,  Hiroaki Oosera ,  Akio Fujita ,  Yusuke Kikuchi

IPC分类号： A63F13/00

CPC分类号： G07F17/34

摘要： Disclosed is a gaming machine. According to the gaming machine, when a combination of symbols relating to a winning is displayed on a one line, the symbols constituting the combination of symbols relating to the winning and symbols constituting a combination of specific symbols in accordance with the combination of symbols relating to the winning are respectively arranged on peripheries of reels so that the combination of specific symbols is displayed on a line different from the one line. In addition, an image display unit of the gaming machine displays a specific image representing a corresponding relationship between a prize in accordance with the combination of symbols relating to the winning and the combination of specific symbols in accordance with the combination of symbols relating to the winning.

摘要翻译： 公开了一种游戏机。 根据游戏机，当在一行上显示与胜利有关的符号的组合时，构成与胜利有关的符号的组合的符号和构成特定符号的组合的符号根据与 获胜分别设置在卷轴的周边，使得特定符号的组合显示在与一条线不同的线上。 此外，游戏机的图像显示单元根据与获胜相关的符号的组合，根据与获胜相关的符号的组合和特定符号的组合，显示表示奖品之间的对应关系的特定图像 。

公开(公告)号：US07876207B2

公开(公告)日：2011-01-25

申请号：US11892827

申请日：2007-08-28

申请人： Hideaki Wada ,  Hirosuke Tabata

发明人： Hideaki Wada ,  Hirosuke Tabata

IPC分类号： B60C23/00

CPC分类号： H04W52/0229 ,  Y02D70/00

摘要： In a wake-up control device for waking up a peripheral circuit such as a transmitter/receiver in a radio communication device, during a standby time in which an RF unit and a processing unit are powered off by a switch, an RF signal is received to produce a detection signal by a detector. The detection signal is transferred to the wake-up controller to be sampled. The header and other fields are detected and counted. A control signal is in turn produced by the respective counts to turn on the switch.

摘要翻译： 在用于在无线电通信设备中唤醒诸如发送器/接收器的外围电路的唤醒控制装置中，在RF单元和处理单元由开关断电的待机时间期间，RF信号被接收 以通过检测器产生检测信号。 检测信号被传送到唤醒控制器进行采样。 标题和其他字段被检测和计数。 控制信号又由相应的计数产生，以便接通开关。

公开(公告)号：US20080055099A1

公开(公告)日：2008-03-06

申请号：US11892827

申请日：2007-08-28

申请人： Hideaki Wada ,  Hirosuke Tabata

发明人： Hideaki Wada ,  Hirosuke Tabata

IPC分类号： G08B21/00

CPC分类号： H04W52/0229 ,  Y02D70/00

摘要： In a wake-up control device for waking up a peripheral circuit such as a transmitter/receiver in a radio communication device, during a standby time in which an RF unit and a processing unit are powered off by a switch, an RF signal is received to produce a detection signal by a detector. The detection signal is transferred to the wake-up controller to be sampled. The header and other fields are detected and counted. A control signal is in turn produced by the respective counts to turn on the switch.

摘要翻译： 在用于在无线电通信设备中唤醒诸如发送器/接收器的外围电路的唤醒控制装置中，在RF单元和处理单元由开关断电的待机时间期间，RF信号被接收 以通过检测器产生检测信号。 检测信号被传送到唤醒控制器进行采样。 标题和其他字段被检测和计数。 控制信号又由相应的计数产生，以便接通开关。

公开(公告)号：US07165183B2

公开(公告)日：2007-01-16

申请号：US10284132

申请日：2002-10-31

申请人： Atsuhiko Okada ,  Hideaki Wada ,  Mitsuaki Watanabe ,  Hajime Iwai ,  Hirosuke Tabata ,  Shingo Kazuma

发明人： Atsuhiko Okada ,  Hideaki Wada ,  Mitsuaki Watanabe ,  Hajime Iwai ,  Hirosuke Tabata ,  Shingo Kazuma

IPC分类号： G06F1/10

CPC分类号： G06F1/324 ,  G06F1/3203 ,  G06F11/00 ,  Y02D10/126

摘要： An interrupt signal EMG is put out to a microprocessor 10 when a thermal monitor 40 detects that a package temperature exceeds a reference. The microprocessor then increases a frequency division value N stored in a frequency division value register 31 of a clock mechanism 30. An inputted clock signal MCK is divided by N to generate a system clock signal SCK. Therefore, the frequency of system clock signal SCK decreases when N increases. Consequently, electricity consumption of each function module 20i decreases and the package temperature is reduced.

摘要翻译： 当热监测器40检测到包装温度超过参考值时，中断信号EMG被送到微处理器10。 然后微处理器增加存储在时钟机构30的分频值寄存器31中的分频值N. 输入的时钟信号MCK除以N以产生系统时钟信号SCK。 因此，当N增加时，系统时钟信号SCK的频率减小。 因此，每个功能模块20i的电力消耗减少，并且封装温度降低。

公开(公告)号：US06191991B1

公开(公告)日：2001-02-20

申请号：US09536764

申请日：2000-03-28

申请人： Hideaki Wada

发明人： Hideaki Wada

IPC分类号： G11C700

CPC分类号： G11C7/1087 ,  G11C7/1006 ,  G11C7/1018 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C2207/107

摘要： In a data rate converter, input data received in series synchronously with an input clock signal is converted into parallel data so as to be written into a memory, and the written parallel data is read from the memory and converted into serial data synchronously with an output clock signal so as to be outputted. Clock pulses of the input clock signal are counted to obtain an input count value. A ready signal is produced based on the input count value for allowing the start of reading the parallel data from the memory. The ready signal has a pulse width greater than two periods of the output clock signal. A trigger signal is produced upon detection of the second leading or trailing edge of the output clock signal within the pulse width of the ready signal. In response to the trigger signal, clock pulses of the output clock signal are counted to obtain an output count value. A read signal is produced based on the output count value for reading the parallel data from the memory.

摘要翻译： 在数据速率转换器中，与输入时钟信号同步地串行接收的输入数据被转换为并行数据，以便被写入存储器，并且从存储器读取并写入的并行数据并将其与输出同步地转换为串行数据 时钟信号输出。 对输入时钟信号的时钟脉冲进行计数以获得输入计数值。 基于输入计数值产生就绪信号，以允许开始从存储器读取并行数据。 就绪信号的脉冲宽度大于输出时钟信号的两个周期。 在就绪信号的脉冲宽度内检测到输出时钟信号的第二前沿或后沿产生触发信号。 响应于触发信号，输出时钟信号的时钟脉冲被计数以获得输出计数值。 基于用于从存储器读取并行数据的输出计数值产生读取信号。

公开(公告)号：US5045638A

公开(公告)日：1991-09-03

申请号：US353773

申请日：1989-05-18

申请人： Hideaki Wada ,  Naoto Kitahara ,  Masami Koshimura ,  Mikiya Ono

发明人： Hideaki Wada ,  Naoto Kitahara ,  Masami Koshimura ,  Mikiya Ono

IPC分类号： H05B6/76 ,  G06F1/18 ,  H05K9/00

CPC分类号： H05K9/0049 ,  G06F1/182 ,  H05K9/0052 ,  H05K9/0088

摘要： This invention relates to an apparatus for shielding electromagnetic radiation which includes a casing made primarily of electromagnetic shielding material and an electromagnetic wave suppressor member having high permeability and/or permittivity. A method for using this apparatus also is described. The suppressor member has a high dielectric loss and/or high magnetic loss at a location close to the place in the casing where electromagnetic waves are less shielded, thereby reducing leakage of undesirable electromagnetic waves from the casing.