公开(公告)号：US20120164815A1

公开(公告)日：2012-06-28

申请号：US13324087

申请日：2011-12-13

申请人： Hidetomo Nishimura

发明人： Hidetomo Nishimura

IPC分类号： H01L21/762

CPC分类号： H01L21/76224 ,  H01L21/31053 ,  H01L21/76229

摘要： There is provided a method of forming an element isolation layer, the method including: forming a pad oxide layer and a nitride layer in succession on a front face of a semiconductor substrate; forming a trench so as to penetrate through the pad oxide layer and the nitride layer and into the semiconductor substrate; forming an in-fill oxide layer so as to fill the trench and cover the nitride layer; polishing the in-fill oxide layer using a first polishing agent so as to leave in-fill oxide layer remaining over the nitride layer; and polishing the in-fill oxide layer using a second polishing agent having a polishing selectivity ratio of the in-fill oxide layer to the nitride layer greater than that of the first polishing agent, so as to expose the nitride layer and flatten the exposed faces of the nitride layer and the in-fill oxide layer.

摘要翻译： 提供一种形成元件隔离层的方法，所述方法包括：在半导体衬底的正面上依次形成焊盘氧化物层和氮化物层; 形成沟槽，以穿过焊盘氧化物层和氮化物层并进入半导体衬底; 形成填充氧化物层，以填充沟槽并覆盖氮化物层; 使用第一抛光剂对填充氧化物层进行抛光，以留下残留在氮化物层上的填充氧化物层; 并且使用具有填充氧化物层与氮化物层的抛光选择比的第二抛光剂比第一抛光剂的抛光选择性比第一抛光剂大的抛光剂，以便露出氮化物层并使曝光的表面变平 的氮化物层和填充氧化物层。

公开(公告)号：US20110207290A1

公开(公告)日：2011-08-25

申请号：US13017507

申请日：2011-01-31

申请人： Hidetomo Nishimura

发明人： Hidetomo Nishimura

IPC分类号： H01L21/76

CPC分类号： H01L21/76224

摘要： A semiconductor device fabrication method deposits a dielectric stress-canceling film on oxide films formed on the surfaces of a semiconductor substrate and its isolation trenches, and partly etches the dielectric stress-canceling film to leave a dielectric base film inside each trench and a dielectric top film outside each trench. The trenches are then filled with a dielectric layer that covers the dielectric top and base films, the upper part of this dielectric layer is removed to expose the dielectric top films, and the dielectric top films are selectively etched, using the trench-filling dielectric layer as an etching mask. In the resulting trench isolation structure, the trenches are completely filled with dielectric material, and stress exerted by the oxide films in the trenches during heat treatment is canceled by opposing stress exerted by the dielectric base films.

摘要翻译： 半导体器件制造方法将形成在半导体衬底及其隔离沟槽的表面上的氧化物膜上的介电应力消除膜沉积，并且部分地蚀刻介电应力消除膜以在每个沟槽内部留下介电基底膜， 每个沟槽之外的电影。 然后用覆盖电介质顶部和基底膜的电介质层填充沟槽，去除该介电层的上部以暴露电介质顶部膜，并且使用沟槽填充介电层选择性地蚀刻电介质顶部膜 作为蚀刻掩模。 在所形成的沟槽隔离结构中，沟槽被绝缘材料完全填充，并且在热处理期间由沟槽中的氧化膜施加的应力被相对于由电介质基膜施加的应力消除。

公开(公告)号：US20060205134A1

公开(公告)日：2006-09-14

申请号：US11276404

申请日：2006-02-28

申请人： Hidetomo NISHIMURA

发明人： Hidetomo NISHIMURA

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L29/66659 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/82385 ,  H01L21/823857 ,  H01L21/823864 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7835

摘要： A method for manufacturing a semiconductor device including sidewall insulating films with different thicknesses includes the steps of (a) selectively forming first and second gate electrode structures on first and second active regions of a silicon substrate respectively, (b) forming a first silicon oxide film on the first and second active regions, (c) forming first and second lightly-doped regions in the first and second active regions respectively, (d) removing the first silicon oxide film formed on the first active region while leaving the first silicon oxide film formed on the second active region, (e) forming an insulating film on the first region and an insulating film on the first silicon oxide film formed on the second active region, and (f) forming a first sidewall insulating film on a first gate electrode structure's sidewall while forming a second sidewall insulating film on a second gate electrode structure's sidewall.

摘要翻译： 一种制造包括具有不同厚度的侧壁绝缘膜的半导体器件的方法包括以下步骤：（a）分别在硅衬底的第一和第二有源区上分别形成第一和第二栅电极结构，（b）形成第一氧化硅膜 在第一和第二有源区上分别形成第一和第二有源区的第一和第二轻掺杂区，（d）除去形成在第一有源区上的第一氧化硅膜，同时留下第一氧化硅膜 形成在所述第二有源区上，（e）在所述第一区域上形成绝缘膜，在所述第二有源区上形成所述第一氧化硅膜上的绝缘膜，以及（f）在第一栅极上形成第一侧壁绝缘膜 结构的侧壁，同时在第二栅电极结构的侧壁上形成第二侧壁绝缘膜。

公开(公告)号：US20080296770A1

公开(公告)日：2008-12-04

申请号：US12153648

申请日：2008-05-22

申请人： Hidetomo Nishimura ,  Katsutoshi Saeki

发明人： Hidetomo Nishimura ,  Katsutoshi Saeki

IPC分类号： H01L23/48

CPC分类号： H01L27/1052 ,  H01L23/485 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device of the present invention includes a semiconductor substrate; a diffusion layer formed about a surface of the semiconductor substrate; a first conductive layer formed on the semiconductor substrate, and an insulating layer formed on the semiconductor substrate after the first conductive layer and the diffusion layer are formed, and a second conductive layer formed on the insulating layer, and a first contact formed in the insulating layer, connecting the first conductive layer to the second conductive layer, and a second contact formed in the insulating layer, connecting the first conductive layer to the diffusion layer. In addition, a part of the diffusion layer extends to a lower portion of the first contact.

摘要翻译： 本发明的半导体器件包括半导体衬底; 形成在半导体衬底的表面周围的扩散层; 形成在半导体衬底上的第一导电层和形成在第一导电层和扩散层之后的半导体衬底上的绝缘层，以及形成在绝缘层上的第二导电层和形成在绝缘层上的第一接触层 将第一导电层连接到第二导电层，以及形成在绝缘层中的第二接触层，将第一导电层连接到扩散层。 此外，扩散层的一部分延伸到第一触点的下部。

公开(公告)号：US06475901B2

公开(公告)日：2002-11-05

申请号：US09984321

申请日：2001-10-29

申请人： Hidetomo Nishimura ,  Makiko Nakamura

发明人： Hidetomo Nishimura ,  Makiko Nakamura

IPC分类号： H01L214763

CPC分类号： H01L21/76897 ,  H01L21/76819 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76837 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device including a semiconductor substrate, and a plurality of first interconnects formed over the semiconductor substrate. A first insulating layer covers the plurality of first interconnects, and a second insulating layer is formed between the plurality of first interconnects. The second insulating layer has substantially the same height as the plurality of first interconnects. An intermediate insulating layer is formed over the second insulating layer.

摘要翻译： 一种半导体器件，包括半导体衬底和形成在半导体衬底上的多个第一互连。 第一绝缘层覆盖多个第一互连，并且在多个第一互连之间形成第二绝缘层。 第二绝缘层具有与多个第一互连件基本相同的高度。 中间绝缘层形成在第二绝缘层上。

公开(公告)号：US4085343A

公开(公告)日：1978-04-18

申请号：US692197

申请日：1976-06-02

申请人： Kunio Hasegawa ,  Hidetomo Nishimura ,  Kiyoshi Yamaguchi

发明人： Kunio Hasegawa ,  Hidetomo Nishimura ,  Kiyoshi Yamaguchi

IPC分类号： H02K55/04 ,  H02K9/00

CPC分类号： H02K55/04 ,  Y02E40/625 ,  Y10S505/878

摘要： A rotor for a rotary electrical machine having a superconductive field winding, wherein thermal resistance means is arranged at contact parts between a damper, which is so disposed as to cover the superconductive field winding, and a damper support which supports the damper from the inner side thereof. A plurality of protuberances are formed on either said damper support or said damper for restricting heat flow between said damper and said damper support. It is possible to cause a cooling medium to flow through interstices which are defined at the contact parts between the damper and the damper support.

摘要翻译： 一种用于具有超导场绕组的旋转电机的转子，其中热阻装置设置在阻挡器之间的接触部分处，所述阻尼器设置成覆盖超导场线圈，以及阻尼器支撑件，其从内侧支撑阻尼器 其中。 在所述阻尼器支撑件或所述阻尼器上形成有多个突起，用于限制所述阻尼器和所述阻尼器支撑件之间的热流。 可以使冷却介质流过限定在阻尼器和阻尼器支撑件之间的接触部分的间隙。