公开(公告)号：US20080296770A1

公开(公告)日：2008-12-04

申请号：US12153648

申请日：2008-05-22

申请人： Hidetomo Nishimura ,  Katsutoshi Saeki

发明人： Hidetomo Nishimura ,  Katsutoshi Saeki

IPC分类号： H01L23/48

CPC分类号： H01L27/1052 ,  H01L23/485 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device of the present invention includes a semiconductor substrate; a diffusion layer formed about a surface of the semiconductor substrate; a first conductive layer formed on the semiconductor substrate, and an insulating layer formed on the semiconductor substrate after the first conductive layer and the diffusion layer are formed, and a second conductive layer formed on the insulating layer, and a first contact formed in the insulating layer, connecting the first conductive layer to the second conductive layer, and a second contact formed in the insulating layer, connecting the first conductive layer to the diffusion layer. In addition, a part of the diffusion layer extends to a lower portion of the first contact.

摘要翻译： 本发明的半导体器件包括半导体衬底; 形成在半导体衬底的表面周围的扩散层; 形成在半导体衬底上的第一导电层和形成在第一导电层和扩散层之后的半导体衬底上的绝缘层，以及形成在绝缘层上的第二导电层和形成在绝缘层上的第一接触层 将第一导电层连接到第二导电层，以及形成在绝缘层中的第二接触层，将第一导电层连接到扩散层。 此外，扩散层的一部分延伸到第一触点的下部。

公开(公告)号：US09042179B2

公开(公告)日：2015-05-26

申请号：US13324559

申请日：2011-12-13

申请人： Katsutoshi Saeki

发明人： Katsutoshi Saeki

IPC分类号： G11C16/04 ,  G11C16/34 ,  G11C16/14 ,  G11C7/06

CPC分类号： G11C16/0466 ,  G11C7/062 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/34

摘要： A method for writing data in a semiconductor storage device and a semiconductor storage device are provided, that can reduce variations in readout current from a sub storage region which serves as a reference cell for the memory cells of the semiconductor storage device, thereby preventing an improper determination from being made when determining the readout current from a memory cell. In the method, data is written on a memory cell in two data write steps by applying voltages to the first and second impurity regions of the memory cell, the voltages being different in magnitude from each other.

摘要翻译： 提供一种在半导体存储装置和半导体存储装置中写入数据的方法，其可以减少作为用于半导体存储装置的存储单元的参考单元的子存储区域的读出电流的变化，从而防止不正当的 当从存储器单元确定读出电流时确定。 在该方法中，通过向存储单元的第一和第二杂质区域施加电压，电压彼此不同，电压在两个数据写入步骤中将数据写入存储单元。

公开(公告)号：US20100244145A1

公开(公告)日：2010-09-30

申请号：US12659780

申请日：2010-03-22

申请人： Katsutoshi Saeki

发明人： Katsutoshi Saeki

IPC分类号： H01L27/088

CPC分类号： H01L29/7885 ,  G11C16/0425 ,  G11C16/10 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11531

摘要： A semiconductor memory device has a low-resistivity semiconductor substrate on which a higher-resistivity semiconductor layer of the same conductivity type is formed. Memory cell transistors are formed in the semiconductor layer. A diffusion region, also of the same conductivity type, is formed below the memory cell transistors. The resistivity of the diffusion region is lower than the resistivity of the semiconductor layer. In the programming of data into the memory cell transistors by hot electron injection, the diffusion region reduces the voltage drop due to current flow from the part of the semiconductor layer near the memory cell transistors into the semiconductor substrate, thereby reducing unwanted elevation of the potential of the semiconductor layer.

摘要翻译： 半导体存储器件具有其上形成相同导电类型的高电阻率半导体层的低电阻率半导体衬底。 存储单元晶体管形成在半导体层中。 在存储单元晶体管的下方形成也具有相同导电类型的扩散区域。 扩散区的电阻率低于半导体层的电阻率。 在通过热电子注入将数据编程到存储单元晶体管中时，扩散区域减小了由于从存储单元晶体管附近的半导体层的部分流入半导体衬底的电流的电压降，从而减少了潜在的不希望的升高 的半导体层。

公开(公告)号：US07696084B2

公开(公告)日：2010-04-13

申请号：US12076054

申请日：2008-03-13

申请人： Katsutoshi Saeki ,  Yoshitaka Satou

发明人： Katsutoshi Saeki ,  Yoshitaka Satou

IPC分类号： H01L21/00

CPC分类号： H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/11573

摘要： A semiconductor device includes a first field effect transistor and a second field effect transistor. The first field effect transistor includes a first gate electrode formed; first impurity diffused areas; and first sidewall portions. The first sidewall portions include a first lower insulation film and a first charge accumulation film. The second field effect transistor includes a second gate electrode; second impurity diffused areas; and second sidewall portions. The second sidewall portions include a second lower insulation film and a second charge accumulation film. The first lower insulation film contains one of a silicon thermal oxide film and a non-doped silicate glass, and the second lower insulation film contains a non-doped silicate glass. The second sidewall portions have a width along a gate longitudinal direction larger than that of the first sidewall portions. The second lower insulation film has a thickness larger than that of the first lower insulation film.

摘要翻译： 半导体器件包括第一场效应晶体管和第二场效应晶体管。 第一场效应晶体管包括形成的第一栅电极; 第一杂质扩散区; 和第一侧壁部分。 第一侧壁部分包括第一下绝缘膜和第一电荷累积膜。 第二场效应晶体管包括第二栅电极; 第二杂质扩散区; 和第二侧壁部分。 第二侧壁部分包括第二下绝缘膜和第二电荷累积膜。 第一下部绝缘膜包含硅热氧化物膜和非掺杂硅酸盐玻璃之一，第二下部绝缘膜含有未掺杂的硅酸盐玻璃。 第二侧壁部分沿着栅极纵向的宽度大于第一侧壁部分的宽度。 第二下绝缘膜的厚度大于第一下绝缘膜的厚度。

公开(公告)号：US20070221981A1

公开(公告)日：2007-09-27

申请号：US11702153

申请日：2007-02-05

申请人： Katsutoshi Saeki

发明人： Katsutoshi Saeki

IPC分类号： H01L29/76

CPC分类号： H01L29/7923 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/513

摘要： A semiconductor memory has a gate electrode and a pair of multilayer memory elements formed on side surfaces of the gate electrode. Each multilayer memory element includes, in sequence from the gate electrode outward, a first silicon oxide layer, a charge trapping silicon nitride layer, a second silicon oxide layer, all with L-shaped cross sections, and a protective silicon nitride layer with an approximately rectangular cross section seated in the L-shape of the second silicon oxide layer. The protective silicon nitride layer protects the charge trapping silicon nitride layer from etching damage during the formation of contact holes without adding to the area occupied by the memory cell.

摘要翻译： 半导体存储器具有栅电极和形成在栅电极的侧表面上的一对多层存储元件。 每个多层存储元件依次从栅电极向外包括第一氧化硅层，电荷陷阱氮化硅层，第二氧化硅层，全部具有L形横截面，以及保护氮化硅层，其具有约 坐在第二氧化硅层的L形中的矩形横截面。 保护氮化硅层保护电荷捕获氮化硅层免于在形成接触孔期间的蚀刻损伤，而不会增加存储单元所占据的面积。

公开(公告)号：US06784482B2

公开(公告)日：2004-08-31

申请号：US10361601

申请日：2003-02-11

申请人： Katsutoshi Saeki

发明人： Katsutoshi Saeki

IPC分类号： H01L2972

CPC分类号： H01L29/42324 ,  H01L21/28273 ,  H01L29/7885

摘要： The nonvolatile semiconductor memory device includes a first conductivity-type semiconductor substrate where an active region is created, a floating gate which is formed on the first conductivity-type semiconductor substrate, and a control gate which is formed on the floating gate. A first conductivity-type high concentration diffused region is formed in the non-overlapping region of the floating gate in the active region.

摘要翻译： 非易失性半导体存储器件包括形成有源区的第一导电型半导体衬底，形成在第一导电型半导体衬底上的浮置栅极和形成在浮置栅极上的控制栅极。 第一导电型高浓度扩散区域形成在有源区域中的浮置栅极的非重叠区域中。

公开(公告)号：US08207611B2

公开(公告)日：2012-06-26

申请号：US12324824

申请日：2008-11-26

申请人： Katsutoshi Saeki

发明人： Katsutoshi Saeki

IPC分类号： H01L23/48

CPC分类号： H01L21/28273 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11531 ,  H01L29/7923

摘要： A semiconductor device including an intermediate insulating film formed over a plurality of first conductors over a semiconductor substrate. Contact holes are formed in the intermediate insulating film over the first conductors, and contact plugs are buried in the contact holes, respectively. A plurality of second conductors are formed over the plurality of contact plugs on the intermediate insulating film, respectively, and are electrically connected to the plurality of first conductors via the contact plugs. In certain regions of the semiconductor device, the contact plugs may terminate within the intermediate insulating film, thereby electrically insulating the second conductors from the first conductors.

摘要翻译： 一种半导体器件，包括在半导体衬底上形成在多个第一导体上的中间绝缘膜。 在第一导体上的中间绝缘膜上形成接触孔，接触孔分别埋在接触孔中。 多个第二导体分别形成在中间绝缘膜上的多个接触插塞上，并且经由接触插头电连接到多个第一导体。 在半导体器件的某些区域中，接触插塞可以终止在中间绝缘膜内，从而使第二导体与第一导体电绝缘。

公开(公告)号：US07863690B2

公开(公告)日：2011-01-04

申请号：US12713524

申请日：2010-02-26

申请人： Katsutoshi Saeki ,  Yoshitaka Satou

发明人： Katsutoshi Saeki ,  Yoshitaka Satou

IPC分类号： H01L21/00

CPC分类号： H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/11573

摘要： A semiconductor device includes a first field effect transistor and a second field effect transistor. The first field effect transistor includes a first gate electrode formed; first impurity diffused areas; and first sidewall portions. The first sidewall portions include a first lower insulation film and a first charge accumulation film. The second field effect transistor includes a second gate electrode; second impurity diffused areas; and second sidewall portions. The second sidewall portions include a second lower insulation film and a second charge accumulation film. The first lower insulation film contains one of a silicon thermal oxide film and a non-doped silicate glass, and the second lower insulation film contains a non-doped silicate glass. The second sidewall portions have a width along a gate longitudinal direction larger than that of the first sidewall portions. The second lower insulation film has a thickness larger than that of the first lower insulation film.

摘要翻译： 半导体器件包括第一场效应晶体管和第二场效应晶体管。 第一场效应晶体管包括形成的第一栅电极; 第一杂质扩散区; 和第一侧壁部分。 第一侧壁部分包括第一下绝缘膜和第一电荷累积膜。 第二场效应晶体管包括第二栅电极; 第二杂质扩散区; 和第二侧壁部分。 第二侧壁部分包括第二下绝缘膜和第二电荷累积膜。 第一下部绝缘膜包含硅热氧化物膜和非掺杂硅酸盐玻璃之一，第二下部绝缘膜含有未掺杂的硅酸盐玻璃。 第二侧壁部分沿着栅极纵向的宽度大于第一侧壁部分的宽度。 第二下绝缘膜的厚度大于第一下绝缘膜的厚度。

公开(公告)号：US07808035B2

公开(公告)日：2010-10-05

申请号：US11702153

申请日：2007-02-05

申请人： Katsutoshi Saeki

发明人： Katsutoshi Saeki

IPC分类号： H01L27/108

CPC分类号： H01L29/7923 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/513

摘要： A semiconductor memory has a gate electrode and a pair of multilayer memory elements formed on side surfaces of the gate electrode. Each multilayer memory element includes, in sequence from the gate electrode outward, a first silicon oxide layer, a charge trapping silicon nitride layer, a second silicon oxide layer, all with L-shaped cross sections, and a protective silicon nitride layer with an approximately rectangular cross section seated in the L-shape of the second silicon oxide layer. The protective silicon nitride layer protects the charge trapping silicon nitride layer from etching damage during the formation of contact holes without adding to the area occupied by the memory cell.

摘要翻译： 半导体存储器具有栅电极和形成在栅电极的侧表面上的一对多层存储元件。 每个多层存储元件依次从栅电极向外包括第一氧化硅层，电荷陷阱氮化硅层，第二氧化硅层，全部具有L形横截面，以及保护氮化硅层，其具有约 坐在第二氧化硅层的L形中的矩形横截面。 保护氮化硅层保护电荷捕获氮化硅层免于在形成接触孔期间的蚀刻损伤，而不会增加存储单元所占据的面积。

公开(公告)号：US20080237730A1

公开(公告)日：2008-10-02

申请号：US12076054

申请日：2008-03-13

申请人： Katsutoshi Saeki ,  Yoshitaka Satou

发明人： Katsutoshi Saeki ,  Yoshitaka Satou

IPC分类号： H01L29/78 ,  H01L21/8238

CPC分类号： H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/11573

摘要： A semiconductor device includes a first field effect transistor and a second field effect transistor. The first field effect transistor includes a first gate electrode formed; first impurity diffused areas; and first sidewall portions. The first sidewall portions include a first lower insulation film and a first charge accumulation film. The second field effect transistor includes a second gate electrode; second impurity diffused areas; and second sidewall portions. The second sidewall portions include a second lower insulation film and a second charge accumulation film. The first lower insulation film contains one of a silicon thermal oxide film and a non-doped silicate glass, and the second lower insulation film contains a non-doped silicate glass. The second sidewall portions have a width along a gate longitudinal direction larger than that of the first sidewall portions. The second lower insulation film has a thickness larger than that of the first lower insulation film.

摘要翻译： 半导体器件包括第一场效应晶体管和第二场效应晶体管。 第一场效应晶体管包括形成的第一栅电极; 第一杂质扩散区; 和第一侧壁部分。 第一侧壁部分包括第一下绝缘膜和第一电荷累积膜。 第二场效应晶体管包括第二栅电极; 第二杂质扩散区; 和第二侧壁部分。 第二侧壁部分包括第二下绝缘膜和第二电荷累积膜。 第一下部绝缘膜包含硅热氧化物膜和非掺杂硅酸盐玻璃之一，第二下部绝缘膜含有未掺杂的硅酸盐玻璃。 第二侧壁部分沿着栅极纵向的宽度大于第一侧壁部分的宽度。 第二下绝缘膜的厚度大于第一下绝缘膜的厚度。