公开(公告)号：US4727265A

公开(公告)日：1988-02-23

申请号：US755910

申请日：1985-07-17

申请人： Hiroaki Nanbu ,  Noriyuki Honma ,  Kunihiko Yamaguchi ,  Kazuo Kanetani ,  Goro Kitsukawa

发明人： Hiroaki Nanbu ,  Noriyuki Honma ,  Kunihiko Yamaguchi ,  Kazuo Kanetani ,  Goro Kitsukawa

IPC分类号： G11C11/414 ,  G11C11/41 ,  H03K17/30 ,  H03K17/60 ,  H03K17/62 ,  H03K17/693 ,  H03K17/16 ,  H03K19/00 ,  H03K19/092 ,  H03L5/00

CPC分类号： H03K17/693 ,  H03K17/603 ,  H03K17/6292

摘要： A semiconductor circuit of a current mode type logic is provided having a reference voltage generating circuit which generates the reference voltage to be applied to the logic circuit in response to a clock signal to latch the state corresponding to an input signal at an instant of the clock signal input. The reference voltage has three levels in response to the voltage levels of the clock signal and the input signal: a middle voltage between the two high and low voltage levels of the input signal when the clock signal is at a first level voltage; a voltage higher than the high voltage level of the input signal when the clock signal is at a second level voltage and the output signal is at a high voltage; and a voltage lower than the low voltage level of the input signal when the clock signal is at a second level voltage and the output signal is at a second level voltage and the output signal is at a low voltage. This semiconductor circuit can relax restrictions on the signal amplitude due to the supply voltage and the saturation of the transistors, and, accordingly, allows processing signals having a much greater amplitude than was previously possible.

摘要翻译： 提供电流模式型逻辑的半导体电路，其具有参考电压产生电路，该参考电压产生电路响应于时钟信号产生要施加到逻辑电路的参考电压，以在时钟瞬间锁存对应于输入信号的状态 信号输入。 参考电压响应于时钟信号和输入信号的电压电平而具有三个电平：当时钟信号处于第一电平电压时，输入信号的两个高电平和低电平电平之间的中间电压; 当所述时钟信号处于第二电平电压并且所述输出信号处于高电压时，所述电压高于所述输入信号的高电压电平; 以及当所述时钟信号处于第二电平电压并且所述输出信号处于第二电平电压且所述输出信号处于低电压时，所述电压低于所述输入信号的低电压电平。 该半导体电路可以放宽由于晶体管的电源电压和饱和度导致的对信号幅度的限制，因此允许处理具有比之前可能的幅度大得多的信号。

公开(公告)号：US4733372A

公开(公告)日：1988-03-22

申请号：US893930

申请日：1986-08-06

申请人： Hiroaki Nanbu ,  Kunihiko Yamaguchi ,  Noriyuki Honma ,  Kazuo Kanetani ,  Motoaki Matumoto ,  Kazuhiko Tani ,  Kenichi Ohata

发明人： Hiroaki Nanbu ,  Kunihiko Yamaguchi ,  Noriyuki Honma ,  Kazuo Kanetani ,  Motoaki Matumoto ,  Kazuhiko Tani ,  Kenichi Ohata

IPC分类号： G11C29/00 ,  G11C8/00

CPC分类号： G11C29/80 ,  G11C29/832 ,  G11C29/84

摘要： Herein disclosed is a bipolar memory having redundancy, which can be produced with a small area. In this semiconductor memory having a body memory for storing data and a spare memory for relief of fault bit of the body memory, a row is selected by cutting fuses in a decoder. Fundamentally signal lines such as word lines are not provided with fuses. Other parts including a power source and a reference voltage source are provided with fuses without decreasing the operating speed accompanied by only a slight increase in the area.

摘要翻译： 这里公开了具有冗余的双极存储器，其可以以小的面积生产。 在具有用于存储数据的身体存储器和用于缓解身体存储器的故障位的备用存储器的该半导体存储器中，通过切割解码器中的熔丝来选择行。 基本上信号线如字线没有提供保险丝。 包括电源和参考电压源在内的其它部件设有保险丝，而不会降低运行速度，同时只有轻微的面积增加。