公开(公告)号：US06400628B2

公开(公告)日：2002-06-04

申请号：US09748139

申请日：2000-12-27

Applicant: Katsumi Dosaka ,  Hiroki Shimano ,  Hiroki Sugano ,  Kazutami Arimoto

Inventor： Katsumi Dosaka ,  Hiroki Shimano ,  Hiroki Sugano ,  Kazutami Arimoto

IPC: G11C702

CPC classification number: H01L27/10882 ,  G11C7/12 ,  G11C7/14 ,  G11C7/18 ,  H01L27/10885 ,  H01L27/10894

Abstract: A dummy bit line is formed from the same layer as and separately from a bit line, and is running in parallel with the bit line. Capacitor is formed on the layer upper than bit line and has a cell plate. An intermediate interconnection is formed on the layer upper than capacitor and is electrically connected to cell plate and dummy bit line. Thus, a semiconductor memory device is obtained in which a cell plate voltage can reliably be fed to a cell plate while preventing the increase of the area of a chip.

Abstract translation: 虚位线与位线相同层分开形成，与位线并行运行。 电容器形成在比位线上方的层上并且具有单元板。 中间互连形成在电容层上方，电连接到单元板和虚拟位线。 因此，获得半导体存储器件，其中可以可靠地将电池板电压馈送到电池板，同时防止芯片面积的增加。

公开(公告)号：US06418075B2

公开(公告)日：2002-07-09

申请号：US09759315

申请日：2001-01-16

Applicant: Hiroki Shimano ,  Kazutami Arimoto ,  Yasuhiro Ishizuka ,  Seizou Furubeppu ,  Hiroki Sugano

Inventor： Hiroki Shimano ,  Kazutami Arimoto ,  Yasuhiro Ishizuka ,  Seizou Furubeppu ,  Hiroki Sugano

IPC: G11C514

CPC classification number: G11C5/145 ,  G11C5/14 ,  G11C5/147

Abstract: A semiconductor integrated circuit in which a logic and a memory are merged, includes a voltage generation unit for generating two or more internal power supply voltages based on two or more external power supply voltages supplied from outside the voltage generation unit with different timings and for furnishing the plurality of internal power supply voltages to the memory. The voltage generation unit includes a standby unit with a small current-feed ability that is always activated, for generating the plurality of internal power supply voltages, and an active unit with a large current-feed ability that is activated as needed, for generating the plurality of internal power supply voltages. An activation control unit prevents the active unit from being activated until all of the plurality of external power supply voltages rise.

Abstract translation: 其中逻辑和存储器被合并的半导体集成电路包括：电压产生单元，用于基于从电压产生单元的外部以不同的定时提供的两个或多个外部电源电压产生两个或多个内部电源电压， 将多个内部电源电压提供给存储器。 电压产生单元包括：始终激活的小电流馈送能力的待机单元，用于产生多个内部电源电压;以及具有大电流馈送能力的有源单元，其根据需要被激活，用于产生 多个内部电源电压。 激活控制单元防止有效单元在所有多个外部电源电压升高之前被激活。

公开(公告)号：US08772694B2

公开(公告)日：2014-07-08

申请号：US13277921

申请日：2011-10-20

Applicant: Hiroki Sugano ,  Fukashi Morishita

Inventor： Hiroki Sugano ,  Fukashi Morishita

IPC: H01L27/146 ,  G01J1/44

CPC classification number: H04N5/3532 ,  H04N5/3745 ,  H04N5/376

Abstract: An image sensor with a small circuit area is provided. In the image sensor, a TX decoder which generates transfer signals TX includes a latch circuit. The latch circuit is set when a corresponding row group is selected and when a set signal is set to an “H” level, and is reset when a reset signal is set to an “L” level. The latch circuit serves also as a voltage level shift circuit which converts the “H” level of a signal from a first power supply voltage into a second power supply voltage. Therefore, plural row groups can be selected by setting plural latch circuits. It is not necessary to provide a voltage level shift circuit separately.

Abstract translation: 提供具有小电路面积的图像传感器。 在图像传感器中，产生传送信号TX <3：0>的TX解码器包括锁存电路。 当选择相应的行组并且将设置信号设置为“H”电平时，锁存电路被设置，并且当复位信号被设置为“L”电平时，锁存电路被复位。 锁存电路还用作电压电平移位电路，其将来自第一电源电压的信号的“H”电平转换为第二电源电压。 因此，可以通过设置多个锁存电路来选择多个行组。 不需要单独提供电压电平移位电路。

公开(公告)号：US06646952B2

公开(公告)日：2003-11-11

申请号：US10122234

申请日：2002-04-16

Applicant: Takashi Tatsumi ,  Junji Mori ,  Hiroki Sugano

Inventor： Takashi Tatsumi ,  Junji Mori ,  Hiroki Sugano

IPC: G11C1100

CPC classification number: H03K19/017581

Abstract: The semiconductor circuit includes a driver that is input with a signal, a driver that is input with a signal, and a driver of which input terminal is connected to output terminals of both the drivers, and of which output terminal is connected to input terminals of both the drivers.

Abstract translation: 半导体电路包括用信号输入的驱动器，输入信号的驱动器，以及驱动器，其输入端子连接到两个驱动器的输出端子，并且其驱动器的输出端子连接到 两个司机。

公开(公告)号：US20120112039A1

公开(公告)日：2012-05-10

申请号：US13277921

申请日：2011-10-20

Applicant: Hiroki Sugano ,  Fukashi Morishita

Inventor： Hiroki Sugano ,  Fukashi Morishita

IPC: H01L27/146

CPC classification number: H04N5/3532 ,  H04N5/3745 ,  H04N5/376

Abstract: An image sensor with a small circuit area is provided. In the image sensor, a TX decoder which generates transfer signals TX includes a latch circuit. The latch circuit is set when a corresponding row group is selected and when a set signal is set to an “H” level, and is reset when a reset signal is set to an “L” level. The latch circuit serves also as a voltage level shift circuit which converts the “H” level of a signal from a first power supply voltage into a second power supply voltage. Therefore, plural row groups can be selected by setting plural latch circuits. It is not necessary to provide a voltage level shift circuit separately.

Abstract translation: 提供具有小电路面积的图像传感器。 在图像传感器中，产生传送信号TX <3：0>的TX解码器包括锁存电路。 当选择相应的行组并且将设置信号设置为“H”电平时，锁存电路被设置，并且当复位信号被设置为“L”电平时，锁存电路被复位。 锁存电路还用作电压电平移位电路，其将来自第一电源电压的信号的“H”电平转换为第二电源电压。 因此，可以通过设置多个锁存电路来选择多个行组。 不需要单独提供电压电平移位电路。