公开(公告)号：US20120112039A1

公开(公告)日：2012-05-10

申请号：US13277921

申请日：2011-10-20

Applicant: Hiroki Sugano ,  Fukashi Morishita

Inventor： Hiroki Sugano ,  Fukashi Morishita

IPC: H01L27/146

CPC classification number: H04N5/3532 ,  H04N5/3745 ,  H04N5/376

Abstract: An image sensor with a small circuit area is provided. In the image sensor, a TX decoder which generates transfer signals TX includes a latch circuit. The latch circuit is set when a corresponding row group is selected and when a set signal is set to an “H” level, and is reset when a reset signal is set to an “L” level. The latch circuit serves also as a voltage level shift circuit which converts the “H” level of a signal from a first power supply voltage into a second power supply voltage. Therefore, plural row groups can be selected by setting plural latch circuits. It is not necessary to provide a voltage level shift circuit separately.

Abstract translation: 提供具有小电路面积的图像传感器。 在图像传感器中，产生传送信号TX <3：0>的TX解码器包括锁存电路。 当选择相应的行组并且将设置信号设置为“H”电平时，锁存电路被设置，并且当复位信号被设置为“L”电平时，锁存电路被复位。 锁存电路还用作电压电平移位电路，其将来自第一电源电压的信号的“H”电平转换为第二电源电压。 因此，可以通过设置多个锁存电路来选择多个行组。 不需要单独提供电压电平移位电路。

公开(公告)号：US08772694B2

公开(公告)日：2014-07-08

申请号：US13277921

申请日：2011-10-20

Applicant: Hiroki Sugano ,  Fukashi Morishita

Inventor： Hiroki Sugano ,  Fukashi Morishita

IPC: H01L27/146 ,  G01J1/44

CPC classification number: H04N5/3532 ,  H04N5/3745 ,  H04N5/376

Abstract: An image sensor with a small circuit area is provided. In the image sensor, a TX decoder which generates transfer signals TX includes a latch circuit. The latch circuit is set when a corresponding row group is selected and when a set signal is set to an “H” level, and is reset when a reset signal is set to an “L” level. The latch circuit serves also as a voltage level shift circuit which converts the “H” level of a signal from a first power supply voltage into a second power supply voltage. Therefore, plural row groups can be selected by setting plural latch circuits. It is not necessary to provide a voltage level shift circuit separately.

Abstract translation: 提供具有小电路面积的图像传感器。 在图像传感器中，产生传送信号TX <3：0>的TX解码器包括锁存电路。 当选择相应的行组并且将设置信号设置为“H”电平时，锁存电路被设置，并且当复位信号被设置为“L”电平时，锁存电路被复位。 锁存电路还用作电压电平移位电路，其将来自第一电源电压的信号的“H”电平转换为第二电源电压。 因此，可以通过设置多个锁存电路来选择多个行组。 不需要单独提供电压电平移位电路。

公开(公告)号：US08638583B2

公开(公告)日：2014-01-28

申请号：US13621078

申请日：2012-09-15

Applicant: Naoya Watanabe ,  Isamu Hayashi ,  Teruhiko Amano ,  Fukashi Morishita ,  Kenji Yoshinaga ,  Mihoko Akiyama ,  Shinya Miyazaki ,  Masakazu Ishibashi ,  Katsumi Dosaka

Inventor： Naoya Watanabe ,  Isamu Hayashi ,  Teruhiko Amano ,  Fukashi Morishita ,  Kenji Yoshinaga ,  Mihoko Akiyama ,  Shinya Miyazaki ,  Masakazu Ishibashi ,  Katsumi Dosaka

IPC: G11C15/00 ,  G11C15/04 ,  G11C7/14 ,  G11C7/06 ,  G11C7/12 ,  G11C7/22

CPC classification number: G11C15/043 ,  G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C7/22 ,  G11C15/04 ,  G11C15/046

Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.

Abstract translation: 包括存储数据位的单位单元的多个比特的条目耦合到匹配线。 匹配线具有一个充电电流，该充电电流的限制电流值小于在一个条目中以一位未命中状态流动的匹配线电流，但大于在一个条目中以全位匹配状态流动的匹配线电流 。 匹配线的预充电电压电平被限制为电源电压的一半或更小的电压电平。 可以减少内容可寻址存储器的搜索周期中的功耗，并且可以提高搜索操作速度。

公开(公告)号：US08154271B2

公开(公告)日：2012-04-10

申请号：US13115327

申请日：2011-05-25

Applicant: Fukashi Morishita

Inventor： Fukashi Morishita

IPC: G05F3/16

CPC classification number: G05F1/465

Abstract: The semiconductor integrated circuit device includes load circuits and internal voltage generators for generating internal source voltages for driving the load circuits. Each of the internal voltage generators includes a reference voltage generating circuit for generating reference voltages, and regulator circuits for generating the internal source voltages with reference to the reference voltages. The regulator circuit is formed over an SOI substrate and includes a preamplifier circuit for detecting and amplifying a difference between each of the internal source voltages and each of the reference voltages, a main amplifier circuit for amplifying the output of the preamplifier circuit and generating a control signal, and a driver circuit for generating the internal source voltage in response to the control signal. An input stage of the main amplifier circuit is configured by MOS transistors coupling the gates and bodies of the MOS transistors.

Abstract translation: 半导体集成电路装置包括用于产生驱动负载电路的内部源电压的负载电路和内部电压发生器。 每个内部电压发生器包括用于产生参考电压的参考电压产生电路和用于参考参考电压产生内部源极电压的调节器电路。 调节器电路形成在SOI衬底上，并且包括用于检测和放大每个内部源电压和每个参考电压之间的差的前置放大器电路，用于放大前置放大器电路的输出并产生控制的主放大器电路 信号和用于响应于控制信号产生内部源电压的驱动器电路。 主放大器电路的输入级由耦合MOS晶体管的栅极和主体的MOS晶体管构成。

公开(公告)号：US20110221419A1

公开(公告)日：2011-09-15

申请号：US13115327

申请日：2011-05-25

Applicant: Fukashi Morishita

Inventor： Fukashi Morishita

IPC: G05F3/16

CPC classification number: G05F1/465

Abstract: The semiconductor integrated circuit device includes load circuits and internal voltage generators for generating internal source voltages for driving the load circuits. Each of the internal voltage generators includes a reference voltage generating circuit for generating reference voltages, and regulator circuits for generating the internal source voltages with reference to the reference voltages. The regulator circuit is formed over an SOI substrate and includes a preamplifier circuit for detecting and amplifying a difference between each of the internal source voltages and each of the reference voltages, a main amplifier circuit for amplifying the output of the preamplifier circuit and generating a control signal, and a driver circuit for generating the internal source voltage in response to the control signal. An input stage of the main amplifier circuit is configured by MOS transistors coupling the gates and bodies of the MOS transistors.

Abstract translation: 半导体集成电路装置包括用于产生驱动负载电路的内部源电压的负载电路和内部电压发生器。 每个内部电压发生器包括用于产生参考电压的参考电压产生电路和用于参考参考电压产生内部源极电压的调节器电路。 调节器电路形成在SOI衬底上，并且包括用于检测和放大每个内部源电压和每个参考电压之间的差的前置放大器电路，用于放大前置放大器电路的输出并产生控制的主放大器电路 信号和用于响应于控制信号产生内部源电压的驱动器电路。 主放大器电路的输入级由耦合MOS晶体管的栅极和主体的MOS晶体管构成。

公开(公告)号：US08004923B2

公开(公告)日：2011-08-23

申请号：US12683838

申请日：2010-01-07

Applicant: Mihoko Akiyama ,  Futoshi Igaue ,  Kenji Yoshinaga ,  Masashi Matsumura ,  Fukashi Morishita

Inventor： Mihoko Akiyama ,  Futoshi Igaue ,  Kenji Yoshinaga ,  Masashi Matsumura ,  Fukashi Morishita

IPC: G11C5/14

CPC classification number: G05F1/468 ,  G11C5/025 ,  G11C5/147

Abstract: A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented.

Abstract translation: 半导体集成电路器件具有设置在每个用于六个存储器宏的电源电路单元的负电压产生电路。 因此，相对于负电压的变化的响应增加。 在待机模式下，通过开关电路连接六个存储器宏的负电压供给线，并且仅在六个电源电路单元的六个负电压产生电路中仅一个电源电路单元的负电压产生电路 活性。 因此，可以防止待机电流的增加。

公开(公告)号：US07977932B2

公开(公告)日：2011-07-12

申请号：US12206907

申请日：2008-09-09

Applicant: Fukashi Morishita

Inventor： Fukashi Morishita

IPC: G05F3/16

CPC classification number: G05F1/465

Abstract: The present invention provides a regulator circuit that can fast-respond to a variation in load current and supply a sufficient drive current so as to be capable of generating a stable internal source voltage. The regulator circuit includes a preamplifier circuit that detects and amplifies a different between a reference voltage and an internal source voltage, a clamp circuit that limits the amplitude of an output of the preamplifier circuit, a main amplifier circuit that amplifies the amplitude-limited output of the preamplifier circuit, and a driver circuit that outputs the internal source voltage according to the output of the main amplifier. Even though the internal source voltage varies abruptly, the regulator circuit does not oscillate owing to the effect of the clamp circuit.

Abstract translation: 本发明提供了一种调节器电路，其能够快速响应负载电流的变化并提供足够的驱动电流，以便能够产生稳定的内部源电压。 调节器电路包括前置放大器电路，其检测和放大参考电压和内部源极电压之间的不同，限制前置放大器电路的输出的幅度的钳位电路，放大限幅输出的主放大器电路 前置放大器电路和根据主放大器的输出输出内部源电压的驱动电路。 即使内部源电压突然变化，调节器电路也不会由于钳位电路的影响而振荡。

公开(公告)号：US07910975B2

公开(公告)日：2011-03-22

申请号：US10593275

申请日：2005-06-03

Applicant: Fukashi Morishita ,  Kazutami Arimoto

Inventor： Fukashi Morishita ,  Kazutami Arimoto

IPC: H01L29/788 ,  H01L27/01 ,  H01L27/12

CPC classification number: G11C11/405 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802

Abstract: The present invention aims at providing a semiconductor memory device that can be manufactured by a MOS process and can realize a stable operation. A storage transistor has impurity diffusion regions, a channel formation region, a charge accumulation node, a gate oxide film, and a gate electrode. The gate electrode is connected to a gate line and the impurity diffusion region is connected to a source line. The storage transistor creates a state where holes are accumulated in the charge accumulation node and a state where the holes are not accumulated in the charge accumulation node to thereby store data “1” and data “0”, respectively. An access transistor has impurity diffusion regions, a channel formation region, a gate oxide film, and a gate electrode. The impurity diffusion region is connected to a bit line.

Abstract translation: 本发明的目的在于提供一种可以通过MOS工艺制造并可实现稳定操作的半导体存储器件。 存储晶体管具有杂质扩散区域，沟道形成区域，电荷累积节点，栅极氧化膜和栅电极。 栅电极连接到栅极线，杂质扩散区连接到源极线。 存储晶体管产生在电荷累积节点中积累空穴的状态和空穴未积累在电荷累积节点中的状态，从而分别存储数据“1”和数据“0”。 存取晶体管具有杂质扩散区，沟道形成区，栅极氧化膜和栅电极。 杂质扩散区域连接到位线。

公开(公告)号：US07906990B2

公开(公告)日：2011-03-15

申请号：US12677745

申请日：2008-09-19

Applicant: Fukashi Morishita

Inventor： Fukashi Morishita

IPC: H01L25/00 ,  H03K19/00 ,  H03K19/20

CPC classification number: H01L27/1203 ,  H01L27/088 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10844 ,  H01L29/7841 ,  H01L29/78615

Abstract: The present invention provides a semiconductor integrated circuit device in which characteristics of an SOI transistor are effectively used to achieve higher speed, higher degree of integration, and also reduction in voltage and power consumption. The semiconductor integrated circuit device according to the present invention has a configuration in which a plurality of external power supply lines and body voltage control lines are alternately arranged in one direction so as to extend over the entire chip, which supply power and a body voltage to logic circuits, an analog circuit and memory circuits. A body voltage control type logic gate is fully applied in the logic circuit, whereas the body voltage control type logic gate is partially applied in the memory circuit.

Abstract translation: 本发明提供一种半导体集成电路器件，其中SOI晶体管的特性被有效地用于实现更高的速度，更高的集成度，并且还降低了电压和功耗。 根据本发明的半导体集成电路器件具有这样的结构，其中多个外部电源线和体电压控制线在一个方向上交替布置，以便在整个芯片上延伸，从而将电源和体电压提供给 逻辑电路，模拟电路和存储器电路。 体电压控制型逻辑门完全应用在逻辑电路中，而体电压控制型逻辑门部分地应用于存储器电路中。

公开(公告)号：US20080252388A1

公开(公告)日：2008-10-16

申请号：US12155876

申请日：2008-06-11

Applicant: Masanobu Kishida ,  Fukashi Morishita

Inventor： Masanobu Kishida ,  Fukashi Morishita

IPC: H03B1/00

CPC classification number: H03K3/0315 ,  H03K17/063

Abstract: The present invention provides a current-limited oscillator capable of performing stable operation even when it is driven with a low power-supply voltage, and a charge pump circuit using the oscillator. A current-limited oscillator has a delay section that includes a plurality of series-connected inverters to delay an output pulse on the basis of a current limiting level indication signal, and the oscillator further includes at least one first transistor that limits a first current between the inverters and a high potential power supply and at least one second transistor that limits a second current between the inverters and a low potential power supply, wherein at least one of the plurality of inverters is configured as a first inverter that is connected with the first transistor and is not connected with the second transistor, and at least another of the plurality of inverters is configured as a second inverter that is not connected with the first transistor and is connected with the second transistor.