公开(公告)号：US5390224A

公开(公告)日：1995-02-14

申请号：US118248

申请日：1993-09-09

申请人： Hiroshi Komatsuda

发明人： Hiroshi Komatsuda

IPC分类号： G06F1/04 ,  G06F11/00 ,  H03K21/08

CPC分类号： G06F1/04

摘要： A clock control apparatus having a basic period clock and a plurality of clocks with different phases from the basic period clock by t/N period, is used with an information processing unit. The apparatus comprising a clock signal generating portion for generating pulses of the basic period clock, a cycle counter for counting the number of pulses of the basic period clock received from the clock signal generating portion when a start command is received and for outputting a cycle counter clock stop signal when the number of pulses becomes a predetermined count value, a control portion for outputting a basic enable period signal for controlling the basic period clock and a delay enable period signal for controlling the t/N period clocks by a flag and the cycle counter clock stop signal, the flag being assignable before the start command is received, a basic period clock enabling portion for receiving pulses of the basic period clock and for outputting the pulses of the basic period clock for a period designated by the basic enable period signal, and a t/N delay period clock enabling portion for generating pulses of the t/N period clocks and for outputting the pulses for a period designated by the delay enable period signal.

摘要翻译： 具有基本周期时钟和具有与基本周期时钟不同相位的多个时钟t / N周期的时钟控制装置与信息处理单元一起使用。 该装置包括用于产生基本周期时钟的脉冲的时钟信号产生部分，一个周期计数器，用于对接收到启动命令时从时钟信号产生部分接收的基本周期时钟的脉冲数进行计数，并输出周期计数器 当脉冲数成为预定计数值时的时钟停止信号，用于输出用于控制基本周期时钟的基本使能周期信号的控制部分和用于通过标志控制t / N周期时钟的延迟使能期间信号， 计数器时钟停止信号，该标志在接收到开始命令之前是可分配的;基本周期时钟使能部分，用于接收基本周期时钟的脉冲，并用于输出由基本周期时间信号指定的周期的基本周期时钟的脉冲 和/ N延迟周期时钟使能部分，用于产生t / N周期时钟的脉冲并输出用于ap的脉冲 延迟使能周期信号指定的周期。

公开(公告)号：US5621395A

公开(公告)日：1997-04-15

申请号：US445731

申请日：1995-05-22

申请人： Akihito Kiyaji ,  Hiroshi Komatsuda ,  Masayuki Katori ,  Kenichi Ishizaka

发明人： Akihito Kiyaji ,  Hiroshi Komatsuda ,  Masayuki Katori ,  Kenichi Ishizaka

IPC分类号： G06F13/00 ,  G06F15/16 ,  G06F15/177 ,  H04L12/70 ,  H04L29/14 ,  G05B23/02

CPC分类号： H04L69/40 ,  Y10T307/477

摘要： A networking apparatus has its switching unit set a path for a data transfer from a processing apparatus on the data origination side to a processing apparatus on the data termination side. In case of a stop in the processing apparatus on the data origination side during the data transfer, the networking apparatus has its offline status detecting unit detect the stop by the presence or absence of an online status indication signal from the processing apparatus on the data origination side and generate an offline status indication signal. The networking apparatus has its controlling unit receive the offline status indication signal, and generate a simulated end-of-data signal, indicating a consummation of a data transfer, for transmission to a switching unit. The networking apparatus has its switching unit detect an end of data by receiving the simulated end-of-data signal, and cancel the path for the data transfer from the processing apparatus on the data origination side to the processing apparatus on the data termination side.

摘要翻译： 网络设备具有其切换单元设置用于从数据发起侧的处理装置到数据终端侧的处理装置的数据传送的路径。 在数据传输期间在数据发起侧的处理装置中停止的情况下，网络装置的离线状态检测单元通过存在或不存在来自处理装置的在线状态指示信号来检测停止 并产生离线状态指示信号。 网络设备的控制单元接收离线状态指示信号，并生成指示完成数据传输的模拟结束数据信号，以传输到交换单元。 网络装置具有其切换单元，通过接收模拟的数据结束信号来检测数据的结束，并且消除从数据发起侧的处理装置到数据终端侧的处理装置的数据传送的路径。

公开(公告)号：US5832261A

公开(公告)日：1998-11-03

申请号：US983075

申请日：1992-11-30

申请人： Kenichi Ishizaka ,  Masayuki Katori ,  Masayuki Ikeda ,  Shigeru Nagasawa ,  Hiroshi Komatsuda

发明人： Kenichi Ishizaka ,  Masayuki Katori ,  Masayuki Ikeda ,  Shigeru Nagasawa ,  Hiroshi Komatsuda

IPC分类号： G06F15/16 ,  G06F9/44 ,  G06F9/52 ,  G06F15/177 ,  G06F15/80

CPC分类号： G06F8/45 ,  G06F15/8007

摘要： In a parallel data processing control system for a parallel computer system having a plurality of computers and an adapter device connecting the computers to each other, a first unit, which is provided in the adapter device, transfers pieces of data processing progress state information to the computers. The pieces of the data processing progress state information respectively indicate data processing progress states of the computers. A second unit, which is provided in each of the computers, holds the pieces of the data processing progress state information. A third unit, which is provided in each of the computers, holds management information indicating a group of computers which share a data process. A fourth unit, which is provided in each of the computers, determines whether or not the computers in the group have completed the data process on the basis of the pieces of the data processing progress state information and the management information.

摘要翻译： 在具有多个计算机的并行计算机系统和将计算机彼此连接的适配器装置的并行数据处理控制系统中，设置在适配器装置中的第一单元将数据处理进度状态信息传送到 电脑。 数据处理进度状态信息分别表示计算机的数据处理进度状态。 设置在每个计算机中的第二单元保存数据处理进度状态信息。 设置在每个计算机中的第三单元保存指示共享数据处理的一组计算机的管理信息。 设置在每台计算机中的第四单元基于数据处理进度状态信息和管理信息来确定组中的计算机是否已经完成数据处理。

公开(公告)号：US5555560A

公开(公告)日：1996-09-10

申请号：US452576

申请日：1995-05-25

申请人： Hiroshi Komatsuda ,  Hidehiko Nishida

发明人： Hiroshi Komatsuda ,  Hidehiko Nishida

IPC分类号： G06F12/06 ,  G06F12/00 ,  G06F13/16 ,  G06F13/14

CPC分类号： G06F13/1631

摘要： A request cancel system is incorporated in a processing system which includes a main storage unit having a plurality of banks, a memory control unit and a plurality of access units, such as central processing units (CPUs), which access the banks of the main storage unit via the memory control unit. A check part in the request cancel system detects whether or not a bank designated by an address of an access request from one of the access units is in use by reading a corresponding bank busy flag from a bank busy flag group. After the check part has determined that a bank designated by an address of a first access request is not busy, a flag is sent to the bank busy flag group to indicate that the bank accessed by the first access request is busy. A second access request to the bank accessed by the first access request can be processed by the check part before the flag is set in the bank busy flag group. A comparator compares the addresses of the first access and second access requests and outputs a coincidence signal when the addresses of the first and second access requests coincide. A request cancel controller cancels the second access request in response to the coincidence signal from the comparator.

摘要翻译： 请求取消系统被并入处理系统中，该处理系统包括具有多个存储体的主存储单元，存储器控制单元和多个访问单元（诸如中央处理单元（CPU）），其访问主存储器 单元通过存储器控制单元。 请求取消系统中的检查部分通过从银行忙标志组读取相应的银行忙碌标志来检测来自其中一个访问单元的访问请求的地址指定的存储体是否在使用。 在支票部分确定由第一访问请求的地址指定的银行不忙时，将标志发送到银行忙标志组，以指示由第一访问请求访问的银行正忙。 通过第一访问请求访问的银行的第二访问请求可以在标志被设置在银行忙标志组之前由检查部件处理。 比较器比较第一接入请求和第二接入请求的地址，并且当第一和第二接入请求的地址一致时输出一致信号。 响应于来自比较器的一致信号，请求取消控制器取消第二访问请求。