公开(公告)号：US07330043B2

公开(公告)日：2008-02-12

申请号：US11079142

申请日：2005-03-15

申请人： Seiji Yamamoto ,  Hirosuke Koumyoji ,  Tohru Yasuda ,  Mikio Ishikawa ,  Isaya Sobue ,  Hajime Sato ,  Chiaki Furukawa ,  Akira Sugiura ,  Akihiro Iwase

发明人： Seiji Yamamoto ,  Hirosuke Koumyoji ,  Tohru Yasuda ,  Mikio Ishikawa ,  Isaya Sobue ,  Hajime Sato ,  Chiaki Furukawa ,  Akira Sugiura ,  Akihiro Iwase

IPC分类号： G01R31/26 ,  G01R31/28

CPC分类号： G01R31/04 ,  H01L2924/0002 ,  H01L2924/00

摘要： A multi-bus semiconductor device and a method of its probing test perform the DC test for individual pads of a device while dealing with an adequate number of devices for simultaneous measurement based on the scheme of input/output pad number compressive test. The semiconductor device includes switch elements SW0-SW4 connected between input/output pads P0-P4 and a testing line L0 so that pads in an arbitrary combination, among the off-probe pads P1-P4 that are not made in contact with the tester probe Pr0, are selected for testing in correspondence to the combination of switch elements that are turned on. The input/output buffers of the pads under test are deactivated to block their internal current paths. The corresponding switch elements are turned on to connect the off-probe pads under test to the probe pad P0 that is made in contact with the tester probe Pr0, and the leak current of the probes is measured with the tester TS.

摘要翻译： 多总线半导体器件及其探测测试方法基于输入/输出焊盘数压缩测试的方案，处理设备的各个焊盘的DC测试，同时处理足够数量的用于同时测量的设备。 半导体器件包括连接在输入/输出焊盘P 0 -P 4和测试线L 0之间的开关元件SW 0 -SW 4，使得不是非探针焊盘P 1 -P 4中的任意组合的焊盘 与测试仪探头Pr 0接触的选择被选择用于与打开的开关元件的组合相对应的测试。 被测试焊盘的输入/输出缓冲器被禁用以阻止其内部电流路径。 将相应的开关元件接通，将被测试的探针焊盘连接到与测试仪探头Pr 0接触的探针焊盘P 0，并用测试仪TS测量探头的漏电流。

公开(公告)号：US20050156589A1

公开(公告)日：2005-07-21

申请号：US11079142

申请日：2005-03-15

申请人： Seiji Yamamoto ,  Hirosuke Koumyoji ,  Tohru Yasuda ,  Mikio Ishikawa ,  Isaya Sobue ,  Hajime Sato ,  Chiaki Furukawa ,  Akira Sugiura ,  Akihiro Iwase

发明人： Seiji Yamamoto ,  Hirosuke Koumyoji ,  Tohru Yasuda ,  Mikio Ishikawa ,  Isaya Sobue ,  Hajime Sato ,  Chiaki Furukawa ,  Akira Sugiura ,  Akihiro Iwase

IPC分类号： G01R31/28 ,  G01R31/04 ,  G11C7/10 ,  H01L21/822 ,  H01L27/04 ,  G01R31/02

CPC分类号： G01R31/04 ,  H01L2924/0002 ,  H01L2924/00

摘要： A multi-bus semiconductor device and a method of its probing test perform the DC test for individual pads of a device while dealing with an adequate number of devices for simultaneous measurement based on the scheme of input/output pad number compressive test. The semiconductor device includes switch elements SW0-SW4 connected between input/output pads P0-P4 and a testing line L0 so that pads in an arbitrary combination, among the off-probe pads P1-P4 that are not made in contact with the tester probe Pr0, are selected for testing in correspondence to the combination of switch elements that are turned on. The input/output buffers of the pads under test are deactivated to block their internal current paths. The corresponding switch elements are turned on to connect the off-probe pads under test to the probe pad P0 that is made in contact with the tester probe Pr0, and the leak current of the probes is measured with the tester TS.

摘要翻译： 多总线半导体器件及其探测测试方法基于输入/输出焊盘数压缩测试的方案，处理设备的各个焊盘的DC测试，同时处理足够数量的用于同时测量的设备。 半导体器件包括连接在输入/输出焊盘P 0 -P 4和测试线L 0之间的开关元件SW 0 -SW 4，使得不是非探针焊盘P 1 -P 4中的任意组合的焊盘 与测试仪探头Pr 0接触的选择被选择用于与打开的开关元件的组合相对应的测试。 被测试焊盘的输入/输出缓冲器被禁用以阻止其内部电流路径。 将相应的开关元件接通，将被测试的探针焊盘连接到与测试仪探头Pr 0接触的探针焊盘P 0，并用测试仪TS测量探头的漏电流。

公开(公告)号：US06885212B2

公开(公告)日：2005-04-26

申请号：US10356489

申请日：2003-02-03

申请人： Seiji Yamamoto ,  Hirosuke Koumyoji ,  Tohru Yasuda ,  Mikio Ishikawa ,  Isaya Sobue ,  Hajime Sato ,  Chiaki Furukawa ,  Akira Sugiura ,  Akihiro Iwase

发明人： Seiji Yamamoto ,  Hirosuke Koumyoji ,  Tohru Yasuda ,  Mikio Ishikawa ,  Isaya Sobue ,  Hajime Sato ,  Chiaki Furukawa ,  Akira Sugiura ,  Akihiro Iwase

IPC分类号： G01R31/28 ,  G01R31/04 ,  G11C7/10 ,  H01L21/822 ,  H01L27/04 ,  G01R31/26

CPC分类号： G01R31/04 ,  H01L2924/0002 ,  H01L2924/00

摘要： A multi-bus semiconductor device and a method of its probing test perform the DC test for individual pads of a device while dealing with an adequate number of devices for simultaneous measurement based on the scheme of input/output pad number compressive test. The semiconductor device includes switch elements SW0-SW4 connected between input/output pads P0-P4 and a testing line L0 so that pads in an arbitrary combination, among the off-probe pads P1-P4 that are not made in contact with the tester probe Pr0, are selected for testing in correspondence to the combination of switch elements that are turned on. The input/output buffers of the pads under test are deactivated to block their internal current paths. The corresponding switch elements are turned on to connect the off-probe pads under test to the probe pad P0 that is made in contact with the tester probe Pr0, and the leak current of the probes is measured with the tester TS.

摘要翻译： 多总线半导体器件及其探测测试方法基于输入/输出焊盘数压缩测试的方案，处理设备的各个焊盘的DC测试，同时处理足够数量的用于同时测量的设备。 半导体器件包括连接在输入/输出焊盘P 0 -P 4和测试线L 0之间的开关元件SW 0 -SW 4，使得不是非探针焊盘P 1 -P 4中的任意组合的焊盘 与测试仪探头Pr 0接触的选择被选择用于与打开的开关元件的组合相对应的测试。 被测试焊盘的输入/输出缓冲器被禁用以阻止其内部电流路径。 将相应的开关元件接通，将被测试的探针焊盘连接到与测试仪探头Pr 0接触的探针焊盘P 0，并用测试仪TS测量探头的漏电流。