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    Swine feed containing vitamin E and spice
    2.
    发明授权
    Swine feed containing vitamin E and spice 失效
    含有维生素E和香料的猪饲料

    公开(公告)号：US5972391A

    公开(公告)日：1999-10-26

    申请号：US890751

    申请日：1997-07-11

    申请人： Hiroyuki Suzuki ,  Hiroyuki Nakao ,  Jino Kikuchi

    发明人： Hiroyuki Suzuki ,  Hiroyuki Nakao ,  Jino Kikuchi

    IPC分类号： A23K1/18 ,  A23K1/16

    CPC分类号： A23K50/00 ,  A23K20/10 ,  A23K20/174 ,  Y10S426/807

    摘要： A swine feed containing as additives a spice and 50-500 ppm of vitamin E. A method for producing pork with improved quality by raising swine with such a feed is also disclosed. When swine are raised with the feed of the present invention, it is possible to produce pork which gives less smell, maintains freshness and quality for prolonged periods, generates less drip, and exhibits good moisture retainability. Moreover, the growth rate of the swine is excellent.

    摘要翻译： 含有作为添加剂的猪饲料和50-500ppm的维生素E.还公开了通过用这种饲料饲养猪来提高质量的猪肉生产方法。 当用本发明的饲料饲养猪时，可以生产较少气味的猪肉，长时间保持新鲜度和质量，产生较少的滴水，并且表现出良好的保湿性。 此外，猪的生长速度非常好。

    Semiconductor memory device
    4.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US06741511B2

    公开(公告)日：2004-05-25

    申请号：US10247324

    申请日：2002-09-20

    申请人： Hiroyuki Nakao

    发明人： Hiroyuki Nakao

    IPC分类号： G11C700

    CPC分类号： G11C29/12005 ,  G11C11/401 ,  G11C29/12 ,  G11C2029/1204

    摘要： When a test mode signal from a control circuit is activated, an operation of a column related circuit is controlled to continuously apply a voltage stress to complementary internal data lines included in the column related circuit. Specifically, a write driver driving a data line is forcedly kept in an inactive state, a sense amplifier is connected to the internal data lines, a column select operation is prohibited and the internal data lines are forcedly, continuously driven in accordance with the write driver, or a voltage setting circuit is connected to the internal data lines and the voltage stress of the internal data lines is accelerated in accordance with the voltage setting circuit during a test. It is possible to continuously apply the voltage stress between complementary data lines of the internal data lines without the need to repeatedly carry out a data write operation, and it is possible to reduce time required for an inter-complementary data line voltage stress test.

    摘要翻译： 当来自控制电路的测试模式信号被激活时，控制列相关电路的操作，以对列列相关电路中包括的互补内部数据线持续施加电压应力。 具体地说，驱动数据线的写入驱动器被强制地保持在非活动状态，读出放大器连接到内部数据线，禁止列选择操作，并且内部数据线被强制地依照写入驱动器连续驱动 或者电压设定电路连接到内部数据线，并且在测试期间根据电压设置电路加速内部数据线的电压应力。 可以在内部数据线的互补数据线之间连续施加电压应力，而不需要重复执行数据写入操作，并且可以减少互补数据线电压应力测试所需的时间。

    Complementary circuit device returnable to normal operation from latch-up phenomenon
    5.
    发明授权
    Complementary circuit device returnable to normal operation from latch-up phenomenon 失效
    补充电路恢复正常操作的补充电路设备

    公开(公告)号：US5140177A

    公开(公告)日：1992-08-18

    申请号：US442754

    申请日：1989-11-29

    申请人： Shinji Suda ,  Hiroshi Kobayashi ,  Katsunobu Hongo ,  Hiroyuki Nakao

    发明人： Shinji Suda ,  Hiroshi Kobayashi ,  Katsunobu Hongo ,  Hiroyuki Nakao

    IPC分类号： H03K17/082 ,  H03K17/22

    CPC分类号： H03K17/223 ,  H03K17/0822

    摘要： A complementary circuit device which cancels a latch-up phenomenon to return to normal operation includes a complementary circuit, a latch-up detection circuit and a reset circuit. The complementary circuit, which is normally started from a prescribed logic state in response to an initial power application of power to the circuit, is susceptible to erroneous restart when the same is resupplied with power immediately after occurrence of a latch-up phenomenon. The latch-up detection circuit detects a latch-up phenomenon occurring in the complementary circuit. The reset circuit resets the complementary circuit to the prescribed logic state in response to an output from the latch-up detection circuit. The complementary circuit is reset again to the prescribed state in a manner similar to the case of initial application of power. The invention facilitates a normal return to operation of a complementary circuit upon cancellation of the latch-up phenomenon.

    Semiconductor memory device having collective writing mode for writing data on row basis
    7.
    发明授权
    Semiconductor memory device having collective writing mode for writing data on row basis 失效
    具有用于以行为基础写入数据的集体写入模式的半导体存储器件

    公开(公告)号：US5896342A

    公开(公告)日：1999-04-20

    申请号：US907778

    申请日：1997-08-11

    申请人： Hiroyuki Nakao

    发明人： Hiroyuki Nakao

    IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C29/14 ,  G11C8/00

    CPC分类号： G11C7/1015 ,  G11C7/1078

    摘要： In a DRAM column decoder, an OR gate receiving a test signal and an output of a column decoder unit circuit is provided corresponding to each column select line. When test signal is at the active "H" level, all column select lines attain the "H" level and all column select gates are rendered conductive, allowing collective writing row by row. A separate circuit for collective writing is not required, so that the layout area is reduced.

    摘要翻译： 在DRAM列解码器中，对应于每个列选择线提供接收测试信号的和门和列解码器单元电路的输出。 当测试信号处于活动“H”电平时，所有列选择线达到“H”电平，所有列选择栅极导通，允许逐行集体写入。 不需要单独的集体写作电路，从而减少了布局面积。