公开(公告)号：US5844914A

公开(公告)日：1998-12-01

申请号：US850807

申请日：1997-05-02

申请人： Heon-Cheol Kim ,  Hong-Sin Jun ,  Chang-Hyun Cho

发明人： Heon-Cheol Kim ,  Hong-Sin Jun ,  Chang-Hyun Cho

IPC分类号： G11C11/401 ,  G01R31/28 ,  G01R31/3181 ,  G11C11/406 ,  G11C29/08 ,  G11C29/12 ,  G11C29/18 ,  G06F11/00

CPC分类号： G11C29/18 ,  G01R31/31813

摘要： A semiconductor memory device and method is shown in which a built-in system test (BIST) circuit determines, based upon the test algorithm and the refresh requirements of a DRAM memory cell array, a refresh point address where the BIST circuit performs a refresh operation on the test data in the memory cell array when the test address reaches the refresh point address. Another embodiment of a semiconductor memory device and method is also shown in which a BIST circuit descrambles the test address and test data before input to a memory circuit which includes address and data scrambling circuits such that the logical test address and test data generated according to a test algorithm matches the physical address and data in the memory cell array.

摘要翻译： 示出了半导体存储器件和方法，其中内置系统测试（BIST）电路基于测试算法和DRAM存储单元阵列的刷新要求确定BIST电路执行刷新操作的刷新点地址 当测试地址到达刷新点地址时，在存储单元阵列中的测试数据。 还示出了半导体存储器件和方法的另一实施例，其中BIST电路在输入到存储器电路之前对测试地址和测试数据进行解扰，该存储器电路包括地址和数据加扰电路，使得逻辑测试地址和根据 测试算法与存储单元阵列中的物理地址和数据相匹配。