公开(公告)号：US20090052252A1

公开(公告)日：2009-02-26

申请号：US12254205

申请日：2008-10-20

申请人： Hyung-seok Kang ,  Eui-gyu Han ,  Gyeong-soo Han ,  Jin-yub Lee ,  Hoo-sung Kim

发明人： Hyung-seok Kang ,  Eui-gyu Han ,  Gyeong-soo Han ,  Jin-yub Lee ,  Hoo-sung Kim

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/0483 ,  G11C16/26

摘要： Provided is a method of improving the read disturb characteristics of a flash memory array. According to the method, in a flash memory array having at least one cell string in which a string selection transistor, a plurality of memory cells, and a ground selection transistor are connected in series, first read voltage is applied to a string selection line connected to a gate of the string selection transistor and a ground selection line connected to a gate of the ground selection transistor. Ground voltage is applied to a word line of a memory cell selected from among the memory cells. Second read voltage is applied to word lines of memory cells, from among the memory cells that are not selected, which are adjacent to the string selection transistor and the ground selection transistor. Then, the first read voltage is applied to the other memory cells that are not selected. The second read voltage is lower than the first read voltage.

摘要翻译： 提供了一种提高闪存阵列的读取干扰特性的方法。 根据该方法，在具有串联选择晶体管，多个存储单元和接地选择晶体管的至少一个单元串的闪速存储器阵列中，将第一读取电压施加到连接的串选择线 到串选择晶体管的栅极和连接到接地选择晶体管的栅极的接地选择线。 将接地电压施加到从存储单元中选择的存储单元的字线。 第二读取电压被施加到与串选择晶体管和地选择晶体管相邻的未被选择的存储单元中的存储单元的字线。 然后，将第一读取电压施加到未被选择的其他存储单元。 第二读取电压低于第一读取电压。

公开(公告)号：US07843736B2

公开(公告)日：2010-11-30

申请号：US12396937

申请日：2009-03-03

申请人： Hyung-Seok Kang ,  Eui-Gyu Han ,  Hoo-Sung Kim

发明人： Hyung-Seok Kang ,  Eui-Gyu Han ,  Hoo-Sung Kim

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C16/28

摘要： Disclosed is a read method of a non-volatile memory device which includes performing a first read operation in which a first read voltage is applied to a selected word line. If a read fail arises at the first read operation, a second read operation is performed in which a second read voltage lower than the first read voltage is applied to the selected word line. If no read fail arises at the second read operation, the read fail generated at the first read operation is cured by performing a program operation.

摘要翻译： 公开了一种非易失性存储器件的读取方法，其包括执行第一读取操作，其中第一读取电压被施加到所选择的字线。 如果在第一读取操作中出现读取失败，则执行第二读取操作，其中低于第一读取电压的第二读取电压被施加到所选择的字线。 如果在第二次读取操作中没有出现读取失败，则通过执行编程操作来固化在第一次读取操作时产生的读取失败。

公开(公告)号：US07813184B2

公开(公告)日：2010-10-12

申请号：US11614413

申请日：2006-12-21

申请人： Hoo-Sung Kim ,  Hyung-Seok Kang ,  Jin-Yub Lee

发明人： Hoo-Sung Kim ,  Hyung-Seok Kang ,  Jin-Yub Lee

IPC分类号： G11C11/00

CPC分类号： G11C16/16 ,  G11C16/0483 ,  G11C16/3445

摘要： Methods of performing multi-block erasing operations on a memory device that includes a plurality of memory blocks are provided. Pursuant to these methods, the rate at which a first voltage that is applied to the memory blocks that are to be erased during the multi-block erasing operation rises is controlled based on the number of memory blocks that are to be erased. The memory device may be a flash memory device, and the first voltage may be an erasing voltage that is applied to a substrate of the flash memory device. The rate at which the first voltage rises may be set so that the substrate of the flash memory device reaches the erasing voltage level at approximately the same time regardless of the number of memory blocks that are to be erased.

摘要翻译： 提供了在包括多个存储器块的存储器件上执行多块擦除操作的方法。 根据这些方法，基于要擦除的存储块的数量来控制施加到在多块擦除操作期间被擦除的存储块的第一电压上升的速率。 存储器件可以是闪存器件，并且第一电压可以是施加到闪存器件的衬底的擦除电压。 可以设置第一电压上升的速率，使得闪存器件的衬底在大致相同的时间达到擦除电压电平，而与要擦除的存储器块的数量无关。

公开(公告)号：US20090231922A1

公开(公告)日：2009-09-17

申请号：US12396937

申请日：2009-03-03

申请人： Hyung-Seok Kang ,  Eui-Gyu Han ,  Hoo-Sung Kim

发明人： Hyung-Seok Kang ,  Eui-Gyu Han ,  Hoo-Sung Kim

IPC分类号： G11C16/06

CPC分类号： G11C16/0483 ,  G11C16/28

摘要： Disclosed is a read method of a non-volatile memory device which includes performing a first read operation in which a first read voltage is applied to a selected word line. If a read fail arises at the first read operation, a second read operation is performed in which a second read voltage lower than the first read voltage is applied to the selected word line. If no read fail arises at the second read operation, the read fail generated at the first read operation is cured by performing a program operation.

摘要翻译： 公开了一种非易失性存储器件的读取方法，其包括执行第一读取操作，其中第一读取电压被施加到所选择的字线。 如果在第一读取操作中出现读取失败，则执行第二读取操作，其中低于第一读取电压的第二读取电压被施加到所选择的字线。 如果在第二次读取操作中没有出现读取失败，则通过执行编程操作来固化在第一次读取操作时产生的读取失败。

公开(公告)号：US07173684B2

公开(公告)日：2007-02-06

申请号：US09893970

申请日：2001-06-29

申请人： Soon Sung Yoo ,  Dong Yeung Kwak ,  Yu Ho Jung ,  Yong Wan Kim ,  Woo Chae Lee ,  Dug Jin Park ,  Hoo Sung Kim

发明人： Soon Sung Yoo ,  Dong Yeung Kwak ,  Yu Ho Jung ,  Yong Wan Kim ,  Woo Chae Lee ,  Dug Jin Park ,  Hoo Sung Kim

IPC分类号： G02F1/1339

CPC分类号： G02F1/1339 ,  G02F1/133351

摘要： A liquid crystal display device, and a fabricating method thereof, that is capable of providing uniform liquid cell gaps. A main seal defines a liquid crystal injection area. A first step coverage-compensating layer is provided between a substrate on which the main seal has been coated and the main seal. A plurality of dummy seals is arranged external to the main seal. A second step coverage-compensating layer having the same thickness as the first step coverage-compensating layer is provided between the substrate on which the dummy seals are arranged and the dummy seals. Accordingly, a main seal and dummy seals having the same thickness produce uniform liquid crystal cell gaps. The liquid crystal display device is beneficially made by a fabrication process employing four or five masks.

摘要翻译： 一种液晶显示装置及其制造方法，其能够提供均匀的液池间隙。 主密封限定了液晶注入区域。 在其上涂覆有主密封件的基板和主密封件之间提供第一级覆盖补偿层。 多个虚拟密封件布置在主密封件的外部。 具有与第一步骤覆盖补偿层相同厚度的第二阶段覆盖补偿层设置在其上布置虚拟密封件的基板和虚拟密封件之间。 因此，具有相同厚度的主密封件和虚拟密封件产生均匀的液晶单元间隙。 液晶显示装置有利地由采用四或五个掩模的制造工艺制成。

公开(公告)号：US08089804B2

公开(公告)日：2012-01-03

申请号：US11810554

申请日：2007-06-06

申请人： Hoo-Sung Kim ,  Eui-Gyu Han

发明人： Hoo-Sung Kim ,  Eui-Gyu Han

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/3418 ,  G11C16/3422 ,  G11C16/3427 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529

摘要： A non-volatile semiconductor memory is configured to monitor for onset of a read disturbance (e.g., due to soft programming) and to carry out operations to protect data therein. A non-volatile semiconductor memory has a memory cell array that includes normal memory cells and a flag memory cell. The flag memory cell is configured to be more susceptible to electrical stress on its retention of data than the normal memory cells. The memory monitors data stored in the flag memory cell to monitor a data retention characteristic of the normal memory cells.

摘要翻译： 非易失性半导体存储器被配置为监视读取干扰的开始（例如，由于软编程），并执行用于保护其中的数据的操作。 非易失性半导体存储器具有包括正常存储单元和标志存储单元的存储单元阵列。 标记存储单元被配置为比其比正常存储器单元更容易受到其对数据保持的电应力。 存储器监视存储在标志存储单元中的数据，以监视正常存储器单元的数据保持特性。

公开(公告)号：US20060028227A1

公开(公告)日：2006-02-09

申请号：US11021182

申请日：2004-12-22

申请人： Kil-Yeon Kim ,  Hoo-Sung Kim

发明人： Kil-Yeon Kim ,  Hoo-Sung Kim

IPC分类号： G01R31/02

CPC分类号： G01R31/2884 ,  G01R31/2831

摘要： According to embodiments of the invention, during a test operation a semiconductor device where an overcurrent flows is detected from among a plurality of semiconductor devices formed on the semiconductor wafer. The power to the semiconductor device where the overcurrent flows may be automatically cut. Furthermore, an overcurrent detection result with respect to semiconductor devices disposed on the wafer is provided to a test apparatus.

摘要翻译： 根据本发明的实施例，在测试操作期间，从半导体晶片上形成的多个半导体器件中检测出过电流流过的半导体器件。 能够自动切断过电流流过的半导体装置的电力。 此外，将相对于设置在晶片上的半导体器件的过电流检测结果提供给测试装置。

公开(公告)号：US06690433B2

公开(公告)日：2004-02-10

申请号：US09923326

申请日：2001-08-08

申请人： Soon-Sung Yoo ,  Dong-Yeung Kwak ,  Hoo-Sung Kim ,  Yu-Ho Jung ,  Yong-Wan Kim ,  Dug-Jin Park ,  Woo-Chae Lee

发明人： Soon-Sung Yoo ,  Dong-Yeung Kwak ,  Hoo-Sung Kim ,  Yu-Ho Jung ,  Yong-Wan Kim ,  Dug-Jin Park ,  Woo-Chae Lee

IPC分类号： G02F11333

CPC分类号： G02F1/136204

摘要： An electrostatic damage preventing apparatus for a thin film transistor array of a liquid crystal display includes a horizontal ground voltage line disposed at a first perimeter portion of the thin film transistor array, a vertical ground voltage line disposed at a second perimeter portion of the thin film transistor array, and a first electrostatic damage-preventing switching device group including parallel connection of at least two electrostatic damage-preventing switching devices to divide and divert an electrostatic voltage applied over the horizontal ground voltage line.

摘要翻译： 一种用于液晶显示器的薄膜晶体管阵列的静电破坏防止装置包括设置在薄膜晶体管阵列的第一周边部分处的水平地电压线，设置在薄膜的第二周边部分的垂直接地电压线 晶体管阵列以及包括至少两个静电损伤防止开关装置的并联连接的第一静电损伤防止开关装置组，以分割和转移施加在水平地电压线上的静电电压。

公开(公告)号：US07705955B2

公开(公告)日：2010-04-27

申请号：US11646531

申请日：2006-12-28

申请人： Soon Sung Yoo ,  Dong Yeung Kwak ,  Yu Ho Jung ,  Yong Wan Kim ,  Woo Chae Lee ,  Dug Jin Park ,  Hoo Sung Kim

发明人： Soon Sung Yoo ,  Dong Yeung Kwak ,  Yu Ho Jung ,  Yong Wan Kim ,  Woo Chae Lee ,  Dug Jin Park ,  Hoo Sung Kim

IPC分类号： G02F1/1339

CPC分类号： G02F1/1339 ,  G02F1/133351

摘要： A liquid crystal display device, and a fabricating method thereof, that is capable of providing uniform liquid cell gaps. A main seal defines a liquid crystal injection area. A first step coverage-compensating layer is provided between a substrate on which the main seal has been coated and the main seal. A plurality of dummy seals is arranged external to the main seal. A second step coverage-compensating layer having the same thickness as the first step coverage-compensating layer is provided between the substrate on which the dummy seals are arranged and the dummy seals. Accordingly, a main seal and dummy seals having the same thickness produce uniform liquid crystal cell gaps. The liquid crystal display device is beneficially made by a fabrication process employing four or five masks.

摘要翻译： 一种液晶显示装置及其制造方法，其能够提供均匀的液池间隙。 主密封限定了液晶注入区域。 在其上涂覆有主密封件的基板和主密封件之间提供第一级覆盖补偿层。 多个虚拟密封件布置在主密封件的外部。 具有与第一步骤覆盖补偿层相同厚度的第二阶段覆盖补偿层设置在其上布置虚拟密封件的基板和虚拟密封件之间。 因此，具有相同厚度的主密封件和虚拟密封件产生均匀的液晶单元间隙。 液晶显示装置有利地由采用四或五个掩模的制造工艺制成。

公开(公告)号：US20080106935A1

公开(公告)日：2008-05-08

申请号：US11810554

申请日：2007-06-06

申请人： Hoo-Sung Kim ,  Eui-Gyu Han

发明人： Hoo-Sung Kim ,  Eui-Gyu Han

IPC分类号： G11C16/34

CPC分类号： G11C16/3418 ,  G11C16/3422 ,  G11C16/3427 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529

摘要： A non-volatile semiconductor memory is configured to monitor for onset of a read disturbance (e.g., due to soft programming) and to carry out operations to protect data therein. A non-volatile semiconductor memory has a memory cell array that includes normal memory cells and a flag memory cell. The flag memory cell is configured to be more susceptible to electrical stress on its retention of data than the normal memory cells. The memory monitors data stored in the flag memory cell to monitor a data retention characteristic of the normal memory cells.

摘要翻译： 非易失性半导体存储器被配置为监视读取干扰的开始（例如，由于软编程），并执行用于保护其中的数据的操作。 非易失性半导体存储器具有包括正常存储单元和标志存储单元的存储单元阵列。 标记存储单元被配置为比其比正常存储器单元更容易受到其对数据保持的电应力。 存储器监视存储在标志存储单元中的数据，以监视正常存储器单元的数据保持特性。