公开(公告)号：US20120124405A1

公开(公告)日：2012-05-17

申请号：US13355519

申请日：2012-01-21

Applicant: Wael William Diab ,  Scott Powell ,  Howard Baumer

Inventor： Wael William Diab ,  Scott Powell ,  Howard Baumer

IPC: G06F1/32

CPC classification number: H04L12/10

Abstract: A system and method for energy savings on a PHY/MAC interface for energy efficient Ethernet. Power savings for a PHY due to low-link utilization can also be realized in the higher layer elements that interface with the PHY. In one embodiment, subrating is implemented on a MAC/PHY interface to match a subrating of the PHY with a remote link partner. This subrating is less than the full capacity rate and can be zero.

Abstract translation: 用于节能以太网PHY / MAC接口节能的系统和方法。 由于低链路利用率，PHY的功率节省也可以在与PHY接口的较高层元件中实现。 在一个实施例中，子帧在MAC / PHY接口上实现，以使PHY的子帧与远程链路伙伴匹配。 该子速率小于全容量率，可以为零。

公开(公告)号：US08111738B2

公开(公告)日：2012-02-07

申请号：US12881108

申请日：2010-09-13

Applicant: Abbas Amirichimeh ,  Howard Baumer ,  John Louie ,  Vasudevan Parthasarathy ,  Linda Ying

Inventor： Abbas Amirichimeh ,  Howard Baumer ,  John Louie ,  Vasudevan Parthasarathy ,  Linda Ying

IPC: H04B1/38 ,  H04L7/00 ,  H04L23/00

CPC classification number: H03K5/135 ,  H04L7/0012 ,  H04L7/0091

Abstract: A transceiver system is disclosed that includes a plurality of transceiver chips. Each transceiver chip includes one or more SERDES cores. Each SERDES core includes one or more SERDES lanes. Each SERDES lane includes a receive channel and a transmit channel. The transmit channel of each SERDES lane is phase-locked with a corresponding receive channel. The transceiver system has the capability of phase-locking a transmit clock signal phase of a transmitting component with a receive clock signal phase of a receiving component that is a part of a different SERDES lane, a different SERDES core, a different substrate, or even a different board. Each SERDES core receives and transmits data to and from external components connected to the SERDES core, such as hard disk drives. A method of transferring data from a first external component coupled to a receive channel to a second external component coupled to a transmit channel is also disclosed.

Abstract translation: 公开了一种收发器系统，其包括多个收发器芯片。 每个收发器芯片包括一个或多个SERDES内核。 每个SERDES核心包​​括一个或多个SERDES通道。 每个SERDES通道包括接收通道和发送通道。 每个SERDES通道的发送通道与相应的接收通道锁相。 收发器系统具有将发送部件的发送时钟信号相位锁定在接收部件的接收时钟信号相位的能力，该接收时钟信号相位是不同SERDES通道的一部分的接收时钟信号相位，不同的SERDES内核，不同的基板，甚至是 一个不同的董事会。 每个SERDES核心接收和传输连接到SERDES核心的外部组件（例如硬盘驱动器）的数据。 还公开了将数据从耦合到接收信道的第一外部组件传送到耦合到发射信道的第二外部组件的方法。

公开(公告)号：US08094590B2

公开(公告)日：2012-01-10

申请号：US12253851

申请日：2008-10-17

Applicant: Abbas Amirichimeh ,  Howard Baumer ,  Dwight Oda

Inventor： Abbas Amirichimeh ,  Howard Baumer ,  Dwight Oda

IPC: H04L13/10

CPC classification number: G06F13/4027 ,  H04L43/50 ,  Y04S40/168

Abstract: A cross link multiplexer bus comprising a plurality of cross link multiplexers and a plurality of interconnects. The plurality of cross link multiplexers has a destination port configured to receive a signal and an origin port configured to produce the signal. The plurality of interconnects has a set of interconnects coupled between a pair of adjacent cross link multiplexers. Preferably, the destination port is in a first cross link multiplexer, the origin port is in a second cross link multiplexer, and the first cross link multiplexer is configured to convey the signal toward the second cross link multiplexer in more than one direction. In an embodiment, the signal is capable of being represented as a series of characters, and a character is capable of being represented as a number of bits. Preferably, the plurality of cross link multiplexers includes a delay buffer to delay conveyance of a first bit so that it remains substantially synchronized with a second bit. Preferably, the set of interconnects includes a first interconnect to convey the first bit and a second interconnect to convey the second bit. The lengths of the first and the second interconnects are substantially equal.

Abstract translation: 一种交叉链路多路复用器总线，包括多个交叉多路复用器和多个互连。 多个交叉多路复用器具有被配置为接收被配置为产生该信号的信号和原始端口的目的地端口。 多个互连具有耦合在一对相邻交叉多路复用器之间的一组互连。 优选地，目的地端口在第一交叉链路多路复用器中，起始端口在第二交叉链路复用器中，并且第一交叉链路多路复用器被配置为在多于一个方向上向第二交叉链路多路复用器传送信号。 在一个实施例中，信号能够被表示为一系列字符，并且字符能够被表示为多个位。 优选地，多个交叉多路复用器包括延迟缓冲器，以延迟第一位的传送，使得其保持与第二位基本上同步。 优选地，该组互连包括用于传送第一位的第一互连和用于传送第二位的第二互连。 第一和第二互连的长度基本相等。

公开(公告)号：US07986622B2

公开(公告)日：2011-07-26

申请号：US11866692

申请日：2007-10-03

Applicant: Howard Frazier ,  Patricia Thaler ,  Ali Ghiasi ,  Howard Baumer

Inventor： Howard Frazier ,  Patricia Thaler ,  Ali Ghiasi ,  Howard Baumer

IPC: H04L1/00 ,  H04L12/26 ,  H04J3/00 ,  H04J3/16 ,  H04J3/22 ,  H04J3/04

CPC classification number: H04L69/14 ,  Y02D50/30

Abstract: Aspects of a system for physical layer aggregation may include one or more switch ICs and/or physical (PHY) layer ICs that enable reception of data packets via a medium access control (MAC) layer protocol entity. Each of the received data packets may be fragmented into a plurality of fragment payloads. Each of the plurality of fragment payloads may be sent to a PHY layer protocol entity instance a physical layer protocol entity instance selected from a plurality of physical layer protocol entity instances.

Abstract translation: 用于物理层聚合的系统的方面可以包括一个或多个开关IC和/或物理（PHY）层IC，其能够经由介质访问控制（MAC）层协议实体接收数据分组。 每个接收到的数据分组可以被分段成多个片段有效载荷。 多个片段有效载荷中的每一个可以被发送到PHY层协议实体实例，从多个物理层协议实体实例中选择的物理层协议实体实例。

公开(公告)号：US20100111100A1

公开(公告)日：2010-05-06

申请号：US12552240

申请日：2009-09-01

Applicant: Howard Baumer

Inventor： Howard Baumer

IPC: H04J3/22 ,  H04J3/24

CPC classification number: H04L27/32 ,  G09G3/2096 ,  G09G5/008 ,  G09G2320/0252 ,  G09G2370/04 ,  G09G2370/10 ,  G09G2370/12 ,  H04L25/14

Abstract: Systems and methods of digital interface translation are described. One embodiment of the invention includes multiple receiver lanes, where at least one of the receiver lanes is configured to receive a data channel at a first data rate and encoded in accordance with an input digital interface standard, an auxiliary channel input configured to receive an auxiliary data channel, and a single transmitter lane configured to output a single data channel at a second data rate and encoded in accordance with an output digital interface standard. In addition, the multilane to single lane digital interface translator is configured to decode the received data into data streams, and interleave the data streams to form packets, the multilane to single lane digital interface translator is configured to insert auxiliary data received via the auxiliary channel input and idle data between the packets to produce an output data stream that is rate matched to the second data rate, and the multilane to single lane digital interface translator is configured to encode the output data stream in accordance with the output digital interface standard.

Abstract translation: 描述了数字接口转换的系统和方法。 本发明的一个实施例包括多个接收机通道，其中至少一个接收机通道被配置为以第一数据速率接收数据信道并根据输入数字接口标准进行编码，辅助信道输入被配置为接收辅助信道 数据信道和单个发射机通道，其被配置为以第二数据速率输出单个数据信道并根据输出数字接口标准进行编码。 另外，多路到单通道数字接口转换器被配置为将接收的数据解码成数据流，并且交织数据流以形成分组，多路到单通道数字接口转换器被配置为插入经由辅助通道接收的辅助数据 输入和空闲数据之间的数据，以产生与第二数据速率匹配的输出数据流，并且多路到单通道数字接口转换器被配置为根据输出数字接口标准对输出数据流进行编码。

公开(公告)号：US07664134B2

公开(公告)日：2010-02-16

申请号：US10667604

申请日：2003-09-23

Applicant: Maurice Caldwell ,  Howard Baumer

Inventor： Maurice Caldwell ,  Howard Baumer

IPC: H04L12/43

CPC classification number: H04L12/42

Abstract: In a network having nodes that operate according to a protocol that defines a node as being in an idle mode when the node is not transmitting or receiving a packet, a method of communicating between nodes during the idle mode. A message formatted according to the protocol is generated. The message is different from messages predefined by the protocol for transmission during the idle mode. For example, the message can comprise a first portion that reports a link status condition. The message can further comprise a second portion that reports a cause of the link status condition. The message is transmitted from a first node of the network when the first node is in the idle mode. The message is received at a second node of the network when the second node is in the idle mode.

Abstract translation: 在具有节点的网络中，在节点不发送或接收分组的情况下，根据协议将节点定义为处于空闲模式的节点，在空闲模式期间在节点之间进行通信的方法。 生成根据协议格式化的消息。 该消息不同于在空闲模式期间用于传输的协议预定义的消息。 例如，消息可以包括报告链路状态条件的第一部分。 消息还可以包括报告链路状态条件的原因的第二部分。 当第一节点处于空闲模式时，该消息从网络的第一节点发送。 当第二节点处于空闲模式时，该消息在网络的第二节点处被接收。

公开(公告)号：US07593457B2

公开(公告)日：2009-09-22

申请号：US10813363

申请日：2004-03-31

Applicant: Abbas Amirichimeh ,  Howard Baumer ,  John Louie ,  Vasudevan Parthasarathy ,  Linda Ying

Inventor： Abbas Amirichimeh ,  Howard Baumer ,  John Louie ,  Vasudevan Parthasarathy ,  Linda Ying

IPC: H04B1/38 ,  H04L7/00

CPC classification number: H03K5/135 ,  H04L7/0012 ,  H04L7/0091

Abstract: A transceiver system is disclosed that includes a plurality of transceiver chips. Each transceiver chip includes one or more SERDES cores. Each SERDES core includes one or more SERDES lanes. Each SERDES lane includes a receive channel and a transmit channel. The transmit channel of each SERDES lane is phase-locked with a corresponding receive channel. The transceiver system has the capability of phase-locking a transmit clock signal phase of a transmitting component with a receive clock signal phase of a receiving component that is a part of a different SERDES lane, a different SERDES core, a different substrate, or even a different board. Each SERDES core receives and transmits data to and from external components connected to the SERDES core, such as hard disk drives. A method of transferring data from a first external component coupled to a receive channel to a second external component coupled to a transmit channel is also disclosed.

Abstract translation: 公开了一种收发器系统，其包括多个收发器芯片。 每个收发器芯片包括一个或多个SERDES内核。 每个SERDES核心包​​括一个或多个SERDES通道。 每个SERDES通道包括接收通道和发送通道。 每个SERDES通道的发送通道与相应的接收通道锁相。 收发器系统具有将发送部件的发送时钟信号相位锁定在接收部件的接收时钟信号相位的能力，该接收时钟信号相位是不同SERDES通道的一部分的接收时钟信号相位，不同的SERDES内核，不同的基板，甚至是 一个不同的董事会。 每个SERDES核心接收和传输连接到SERDES核心的外部组件（例如硬盘驱动器）的数据。 还公开了将数据从耦合到接收信道的第一外部组件传送到耦合到发射信道的第二外部组件的方法。

公开(公告)号：US20050286669A1

公开(公告)日：2005-12-29

申请号：US10876602

申请日：2004-06-28

Applicant: Aaron Buchwald ,  Michael Le ,  Hui Wang ,  Howard Baumer ,  Pieter Vorenkamp

Inventor： Aaron Buchwald ,  Michael Le ,  Hui Wang ,  Howard Baumer ,  Pieter Vorenkamp

IPC: H04L7/00 ,  H04L25/20

CPC classification number: H04L7/0091 ,  H04L7/0025 ,  H04L7/0029 ,  H04L25/20

Abstract: A system and method is provided for phase interpolator based transmission clock control. The system includes a transmitter having a phase interpolator coupled to a master timing generator and a transmission module. The phase interpolator is also coupled to a receiver interpolator control module and/or an external interpolator control module. When the system is operating in repeat mode, the transmitter phase interpolator receives a control signal from a receiver interpolator control module. The transmitter phase interpolator uses the signal to synchronize the transmission clock to the sampling clock. When the system is operating in test mode, a user defines a transmission data profile in an external interpolator control module. The external interpolator control module generates a control signal based on the profile. The transmitter phase interpolator uses the signal to generate a transmission clock that is used by the transmission module to generate a data stream having the desired profile.

Abstract translation: 提供了一种用于基于相位插值器的传输时钟控制的系统和方法。 该系统包括具有耦合到主定时发生器和传输模块的相位插值器的发射机。 相位插值器还耦合到接收器插值器控制模块和/或外部插值器控制模块。 当系统以重复模式运行时，发射机相位插值器从接收器插值器控制模块接收控制信号。 发射机相位内插器使用信号将传输时钟同步到采样时钟。 当系统在测试模式下操作时，用户在外部插值器控制模块中定义传输数据简档。 外部内插器控制模块基于轮廓生成控制信号。 发射机相位内插器使用该信号来生成传输模块使用的传输时钟，以生成具有所需简档的数据流。

公开(公告)号：US20050188284A1

公开(公告)日：2005-08-25

申请号：US10767729

申请日：2004-01-30

Applicant: Jay Proano ,  Howard Baumer ,  Chung-Jue Chen ,  Ali Ghiasi ,  Vasudevan Parthasarathy ,  Rajesh Satapathy ,  Linda Ying

Inventor： Jay Proano ,  Howard Baumer ,  Chung-Jue Chen ,  Ali Ghiasi ,  Vasudevan Parthasarathy ,  Rajesh Satapathy ,  Linda Ying

IPC: G06F11/00

CPC classification number: H04L43/022 ,  H04L43/0811 ,  H04L43/0823 ,  H04L43/16

Abstract: A method is presented that monitors the quality of a communications channel. The method includes receiving a data signal and establishing a zero reference phase of the received data signal. The method further includes generating a phase-shifted data signal by phase shifting the received data signal relative to the zero reference phase, and sampling the phase-shifted data signal for one or more phase-shift positions. A zero reference phase is reestablished between sampling at each of the phase-shift positions. The method also includes detecting bit errors in the phase-shifted data signal at each of the phase-shift positions in order to provide a communications channel quality measurement. In an embodiment, the method includes generating an eye diagram according to a count of detected bit errors relative to a count of detected bits. The eye diagram characterizes the quality of the communications channel.

Abstract translation: 提出了一种监测通信信道质量的方法。 该方法包括接收数据信号并建立接收数据信号的零参考相位。 该方法还包括通过相对于零参考相位相移所接收的数据信号来产生相移数据信号，并对一个或多个相移位置的相移数据信号进行采样。 在每个相移位置的采样之间重新建立零参考相位。 该方法还包括检测每个相移位置处的相移数据信号中的位错误，以提供通信信道质量测量。 在一个实施例中，该方法包括根据检测到的比特错误的计数相对于检测到的比特的计数来生成眼图。 眼图描绘了通信信道的质量。

公开(公告)号：US06930621B2

公开(公告)日：2005-08-16

申请号：US10894103

申请日：2004-07-19

Applicant: Martin Lund ,  Howard Baumer

Inventor： Martin Lund ,  Howard Baumer

IPC: H04L9/06 ,  H04L25/14 ,  H04L25/49 ,  H03M7/40

CPC classification number: H04L25/4908 ,  H04L25/14

Abstract: Disclosed herein is a method and system for providing a secondary communication channel overlaid on a primary communication channel using an enhanced encoding method to effectively expand the utilized information capacity of the primary communication channel. Aspects of the invention may include encoding a portion of at least a first word of one or more data packets in a datastream. A running disparity of the encoded word may be reversed. Hence, if an encoded running disparity of an encoded word is RD positive, i.e., RD(+), then the running disparity is reversed to RD negative, i.e., RD(−). Similarly, if an encoded running disparity is RD negative, i.e., RD(−), then the running disparity is reversed to RD positive, i.e., RD(+). The word may be a data word, control word, or an idle word corresponding to a data packet, a control packet, and an idle packet, respectively.

Abstract translation: 本文公开了一种用于使用增强编码方法提供覆盖在主要通信信道上的辅助通信信道以有效扩展主要通信信道的利用信息容量的方法和系统。 本发明的方面可以包括编码数据流中的一个或多个数据分组的至少第一个单词的一部分。 编码字的运行差异可能会相反。 因此，如果编码字的编码运行差异为RD正，即RD（+），则运行视差被反转为RD负，即RD（ - ）。 类似地，如果编码的运行差异为RD负，即RD（ - ），则运行视差被反转为RD正，即RD（+）。 该单词可以分别是与数据分组，控制分组和空闲分组对应的数据字，控制字或空闲字。