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    Method and apparatus for determining duty cycle of a clock in a circuit using a configurable phase locked loop
    1.
    发明授权
    Method and apparatus for determining duty cycle of a clock in a circuit using a configurable phase locked loop 有权
    用于使用可配置锁相环确定电路中的时钟占空比的方法和装置

    公开(公告)号：US08552780B2

    公开(公告)日：2013-10-08

    申请号：US13269678

    申请日：2011-10-10

    申请人： Thayl D. Zohner ,  Douglas A. Chandler ,  Jae-Hu Kim

    发明人： Thayl D. Zohner ,  Douglas A. Chandler ,  Jae-Hu Kim

    IPC分类号： H03H11/16

    CPC分类号： H03K5/1565

    摘要： An embodiment of the invention discloses phase shifting a second clock signal by a phase increment with respect to a first clock signal, where the first clock signal and the second clock signal have the same periods. The first clock signal is sampled with the second clock signal, and the output of the sample indicates whether the sample of the first clock signal is at a logic one state or a logic zero state. A count of logic one samples is incremented if the sample of the first clock signal is at a logic one state. The process of phase shifting the second clock signal and sampling the first clock signal is repetitively performed to a maximum number of samples.

    摘要翻译： 本发明的实施例公开了相对于第一时钟信号将第二时钟信号相移相位增量，其中第一时钟信号和第二时钟信号具有相同的周期。 第一时钟信号用第二时钟信号采样，并且采样的输出指示第一时钟信号的采样是处于逻辑1状态还是逻辑零状态。 如果第一个时钟信号的采样处于逻辑1状态，逻辑1个样本的计数将递增。 对第二时钟信号进行相移并对第一时钟信号进行采样的过程被重复地执行到最大数量的采样。

    System for determining pluggable memory characteristics employing a status register to provide information in response to a preset field of an address
    2.
    发明授权
    System for determining pluggable memory characteristics employing a status register to provide information in response to a preset field of an address 失效
    用于确定可插拔存储器特性的系统，其采用状态寄存器来提供响应于地址的预设字段的信息

    公开(公告)号：US5253357A

    公开(公告)日：1993-10-12

    申请号：US715077

    申请日：1991-06-13

    申请人： Greg L. Allen ,  Jae-Hu Kim ,  Lynn R. Watson

    发明人： Greg L. Allen ,  Jae-Hu Kim ,  Lynn R. Watson

    IPC分类号： G06F12/06

    CPC分类号： G06F12/0684

    摘要： A system is described that includes an arithmetic logic unit that senses the presence of a circuit module in a connector, wherein one type of circuit module, if present, automatically provides a set of signals on a predetermined pin set that indicates characteristics of the circuit module. The system also includes circuitry that enables the determination of the presence of other types of pluggable circuit modules in the connector. The circuitry comprises a latch circuit for holding a received address for the circuit module. In the received address, a preset field of bits is present which identifies a field in a status register. The status register stores n fields of information defining the characteristics of the pluggable circuit module and is responsive to the preset field of bits to provide signals on the predetermined pin set indicating the information.

    METHOD AND APPARATUS FOR DETERMINING DUTY CYCLE OF A CLOCK IN A CIRCUIT USING A CONFIGURABLE PHASE LOCKED LOOP
    3.
    发明申请
    METHOD AND APPARATUS FOR DETERMINING DUTY CYCLE OF A CLOCK IN A CIRCUIT USING A CONFIGURABLE PHASE LOCKED LOOP 有权
    使用可配置相位锁定环路确定电路中的时钟占空比的方法和装置

    公开(公告)号：US20130088270A1

    公开(公告)日：2013-04-11

    申请号：US13269678

    申请日：2011-10-10

    申请人： Thayl D. Zohner ,  Douglas A. Chandler ,  Jae-Hu Kim

    发明人： Thayl D. Zohner ,  Douglas A. Chandler ,  Jae-Hu Kim

    IPC分类号： H03L7/06

    CPC分类号： H03K5/1565

    摘要： An embodiment of the invention discloses phase shifting a second clock signal by a phase increment with respect to a first clock signal, where the first clock signal and the second clock signal have the same periods. The first clock signal is sampled with the second clock signal, and the output of the sample indicates whether the sample of the first clock signal is at a logic one state or a logic zero state. A count of logic one samples is incremented if the sample of the first clock signal is at a logic one state. The process of phase shifting the second clock signal and sampling the first clock signal is repetitively performed to a maximum number of samples.

    摘要翻译： 本发明的实施例公开了相对于第一时钟信号将第二时钟信号相移相位增量，其中第一时钟信号和第二时钟信号具有相同的周期。 第一时钟信号用第二时钟信号采样，并且采样的输出指示第一时钟信号的采样是处于逻辑1状态还是逻辑零状态。 如果第一个时钟信号的采样处于逻辑1状态，逻辑1个样本的计数将递增。 对第二时钟信号进行相移并对第一时钟信号进行采样的过程被重复地执行到最大数量的采样。