公开(公告)号：US20240298406A1

公开(公告)日：2024-09-05

申请号：US18591021

申请日：2024-02-29

Applicant: IBIDEN CO., LTD.

Inventor： Jun SAKAI ,  Kyohei YOSHIKAWA ,  Shunya HATANAKA

IPC: H05K1/11 ,  H05K1/02 ,  H05K1/03

CPC classification number: H05K1/112 ,  H05K1/0221 ,  H05K1/0222 ,  H05K1/0306 ,  H05K2201/0209 ,  H05K2201/09518 ,  H05K2201/10977

Abstract: A printed wiring board includes a first conductor layer, a resin insulating layer formed on the first conductor layer, a second conductor layer formed on the resin insulating layer and including a seed layer and a metal layer on the seed layer, a via conductor formed in the resin insulating layer such that the via conductor is connecting the first conductor layer and the second conductor layer, and a base layer formed on the resin insulating layer and including resin and one of iron and chromium in a range of 0.2 at % to 5.0 at % with respect to the resin such that the base layer includes part formed between the resin insulating layer and the seed layer.

公开(公告)号：US20240264219A1

公开(公告)日：2024-08-08

申请号：US18431470

申请日：2024-02-02

Applicant: MPI CORPORATION

Inventor： SHIH-CHING CHEN ,  JUN-LIANG LAI

IPC: G01R31/26 ,  H05K1/11 ,  H05K1/18 ,  H05K3/00

CPC classification number: G01R31/2601 ,  H05K1/112 ,  H05K1/181 ,  H05K3/0058 ,  H05K3/0094

Abstract: A circuit board for a semiconductor testing includes first and second substrates, first and second insulating dielectric layers attached to the lower surface of the first substrate and the upper surface of the second substrate respectively and attached to each other, and electrically conductive fillers disposed in first and second through holes of the first and second insulating dielectric layers and electrically connected with first and second electrically conductive pads of the first and second substrates. For the first through holes, compared with the upper ends thereof, the lower ends thereof have larger width or smaller interval. For the second through holes, compared with the lower ends thereof, the upper ends thereof have larger width or smaller interval. A method of manufacturing the circuit board is also disclosed. Accordingly, an alignment problem in connecting substrates by the insulating dielectric layer may be improved, thereby enhancing the circuit integrity.

公开(公告)号：US20240215163A1

公开(公告)日：2024-06-27

申请号：US18089489

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Onur OZKAN ,  Jacob VEHONSKY ,  Vinith BEJUGAM ,  Nicholas S. HAEHN ,  Andrea NICOLAS FLORES ,  Mao-Feng TSENG

IPC: H05K1/11 ,  H05K1/03 ,  H05K1/18

CPC classification number: H05K1/112 ,  H05K1/0306 ,  H05K1/183 ,  H01L23/49838

Abstract: Embodiments disclosed herein include a package core. In an embodiment, the package core comprises a substrate with a first surface and a second surface opposite from the first surface. In an embodiment, the substrate comprise glass. In an embodiment, a via is provided through the substrate, where the via is electrically conductive. In an embodiment, a recess is formed into the first surface of the substrate, and a trace is embedded in the recess. In an embodiment, the trace is electrically conductive.

公开(公告)号：US11997901B2

公开(公告)日：2024-05-28

申请号：US18162136

申请日：2023-01-31

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Byoungyong Kim ,  Seunghwa Ha ,  Seungsoo Ryu ,  Sanghyeon Song ,  Jeongdo Yang ,  Jungyun Jo ,  Jeongho Hwang

IPC: H10K59/13 ,  G02F1/13 ,  G02F1/1345 ,  H05K1/11 ,  H05K3/32 ,  H10K50/844 ,  H10K59/131 ,  H10K71/00

CPC classification number: H10K59/131 ,  G02F1/13458 ,  H05K1/111 ,  H05K1/112 ,  H05K3/32 ,  H05K3/328 ,  H10K50/844 ,  H10K71/00 ,  H05K2201/0373 ,  H05K2201/09845 ,  H05K2203/0285 ,  Y02P70/50

Abstract: A display apparatus includes a display panel having a display substrate on which a plurality of pad terminals is disposed, and a driving unit having a plurality of driving terminals electrically connected to the plurality of pad terminals. Each of the plurality of pad terminals includes a stepped groove that faces a corresponding driving terminal of the plurality of driving terminals or each of the plurality of pad terminals includes an opening hole that faces the corresponding driving terminal of the plurality of driving terminals.

公开(公告)号：US11990438B2

公开(公告)日：2024-05-21

申请号：US17984748

申请日：2022-11-10

Applicant: X Display Company Technology Limited

Inventor： Carl Prevatte ,  Christopher Bower ,  Ronald S. Cok ,  Matthew Meitl

IPC: H01L23/00 ,  H01L21/48 ,  H05K1/11 ,  H05K3/30 ,  H05K3/34

CPC classification number: H01L24/11 ,  H01L24/08 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H05K1/112 ,  H05K3/3436 ,  H01L21/4803 ,  H01L21/4846 ,  H01L2224/1144 ,  H01L2224/11466 ,  H01L2224/13017 ,  H01L2224/13023 ,  H01L2224/1357 ,  H01L2224/1403 ,  H01L2224/1412 ,  H01L2224/1418 ,  H01L2224/16227 ,  H01L2224/1624 ,  H01L2224/17107 ,  H01L2924/12041 ,  H01L2924/12043 ,  H01L2924/12044 ,  H01L2924/1304 ,  H05K3/305 ,  H05K2201/09409 ,  H05K2201/09472 ,  H05K2201/0979 ,  H05K2201/10143 ,  H01L2924/12041 ,  H01L2924/00012 ,  H01L2924/12044 ,  H01L2924/00012 ,  H01L2924/12043 ,  H01L2924/00012 ,  H01L2924/1304 ,  H01L2924/00012

Abstract: A component includes a plurality of electrical connections on a process side opposed to a back side of the component. Each electrical connection includes an electrically conductive multi-layer connection post protruding from the process side. A printed structure includes a destination substrate and one or more components. The destination substrate has two or more electrical contacts and each connection post is in contact with, extends into, or extends through an electrical contact of the destination substrate to electrically connect the electrical contacts to the connection posts. The connection posts or electrical contacts are deformed. Two or more connection posts can be electrically connected to a common electrical contact.

公开(公告)号：US11950366B2

公开(公告)日：2024-04-02

申请号：US17635968

申请日：2020-09-03

Applicant: TDK CORPORATION

Inventor： Kazuhiro Hagita ,  Yoshiaki Ishikawa ,  Masaharu Moritsugu

IPC: H05K1/18 ,  H05K1/11

CPC classification number: H05K1/181 ,  H05K1/112 ,  H05K2201/10515

Abstract: An electronic component mounting structure is an electronic component mounting structure in which an electronic component group is mounted on a substrate, and a pattern constituting a part of a current path between the inflow port and the outflow port, the electronic component group includes a plurality of electronic components connected between the inflow port and the outflow port, each of the electronic components has a current inflow terminal electrically connected to the inflow port and a current outflow terminal electrically connected to the outflow port, and one of a first spatial distance group and a second spatial distance group has equal spatial distances within the one spatial distance group, and the first spatial distance group includes spatial distances between the inflow port and the inflow terminals, and the second spatial distance group includes spatial distances between the outflow port and the outflow terminals.

公开(公告)号：US20240063110A1

公开(公告)日：2024-02-22

申请号：US18492816

申请日：2023-10-24

Applicant: CHUN-MING LIN

Inventor： CHUN-MING LIN

IPC: H01L23/498 ,  C25D7/12 ,  H01L21/48 ,  C25D3/38 ,  H05K1/11 ,  H05K1/09

CPC classification number: H01L23/49866 ,  H01L23/49822 ,  C25D7/12 ,  H01L21/4857 ,  C25D3/38 ,  H01L23/49827 ,  H05K1/112 ,  H05K1/09 ,  H05K1/115 ,  H05K2201/0364 ,  H05K2201/095 ,  H05K2201/09509 ,  H05K1/18

Abstract: The present disclosure provides a method for forming a multilayer wiring structure, which includes: forming a patterned copper-phosphorous alloy layer over a carrier by performing a plating operation, and forming a dielectric layer over the patterned copper-phosphorous alloy layer. The forming the patterned copper-phosphorous alloy layer includes providing a plating solution having a copper source and a phosphorous source.

公开(公告)号：US11895780B2

公开(公告)日：2024-02-06

申请号：US17194323

申请日：2021-03-08

Applicant: Unimicron Technology Corp.

Inventor： Kai-Ming Yang ,  Chen-Hao Lin ,  Wang-Hsiang Tsai ,  Cheng-Ta Ko

IPC: H05K3/46 ,  H05K3/40 ,  H01L23/538 ,  H01L21/768 ,  H01L21/48 ,  H05K1/11 ,  H05K1/18 ,  H05K1/14 ,  H01L23/14 ,  H01L23/15 ,  H01L23/498 ,  H01L23/36 ,  H01L23/00 ,  H01L21/683 ,  H05K1/02

CPC classification number: H05K3/4038 ,  H01L21/486 ,  H01L21/4846 ,  H01L21/4857 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/15 ,  H01L23/36 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H05K1/11 ,  H05K1/112 ,  H05K1/142 ,  H05K1/183 ,  H05K3/4644 ,  H05K3/4673 ,  H01L23/145 ,  H01L23/49816 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/04105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/96 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/37001 ,  H05K1/0271 ,  H05K3/4682 ,  H05K3/4694 ,  H05K2201/10674 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49165 ,  H01L2924/15311 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00014 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00014 ,  H01L2224/131 ,  H01L2924/014

Abstract: A method of manufacturing package structures includes providing a carrier including a supporting layer, a metal layer, and a release layer between the supporting layer and the metal layer at first. Afterwards, a composite layer of a non-conductor inorganic material and an organic material is disposed on the metal layer. Then, a chip embedded substrate is bonded on the composite layer. Afterwards, an insulating protective layer having openings is formed on the circuit layer structure and exposes parts of the circuit layer structure in the openings. Afterwards, the supporting layer and the release layer are removed to form two package substrates. Then, each of the package substrates is cut.

公开(公告)号：US11864317B2

公开(公告)日：2024-01-02

申请号：US17107953

申请日：2020-12-01

Applicant: NICHIA CORPORATION

Inventor： Masaaki Katsumata ,  Koji Taguchi ,  Norifumi Sasaoka ,  Yosuke Noda

IPC: H01L23/48 ,  H01L23/498 ,  H01L33/62 ,  H05K1/09 ,  H05K3/00 ,  H05K3/40 ,  H05K1/11 ,  H01L21/48

CPC classification number: H05K1/115 ,  H01L21/486 ,  H01L21/4846 ,  H01L23/481 ,  H01L23/49822 ,  H01L33/62 ,  H05K1/095 ,  H05K3/0094 ,  H05K3/4038 ,  H05K3/4069 ,  H01L2933/0066 ,  H05K1/112 ,  H05K2201/09454 ,  H05K2201/09572 ,  H05K2201/09854 ,  H05K2201/10106 ,  H05K2203/0126 ,  H05K2203/0139 ,  H05K2203/0278 ,  H05K2203/1105

Abstract: A method of manufacturing a circuit substrate includes forming, in an insulating substrate and circuit patterns that are provided on a first surface and a second surface of the insulating substrate, a through-hole penetrating the insulating substrate and the circuit patterns, where the circuit patterns contain Cu as a main component. The method includes filling, in the through-hole, an electrically conductive paste that is a melting-point shift electrically conductive paste including Sn—Bi solder powder, Cu powder, and resin, and forming a protrusion obtained by causing the electrically conductive paste to protrude from the through-hole. The method further includes performing pressure treatment on the protrusion near the through-hole; and performing heat treatment on the insulating substrate whose protrusion is subjected to the pressure treatment and causing the circuit patterns and the electrically conductive paste to be electrically connected with each other.

公开(公告)号：US20230397342A1

公开(公告)日：2023-12-07

申请号：US18324632

申请日：2023-05-26

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Masayuki Mizuno

IPC: H05K3/46 ,  H05K3/20 ,  H05K1/11 ,  H01L23/498

CPC classification number: H05K3/4644 ,  H05K3/205 ,  H05K1/112 ,  H01L23/49822 ,  H05K2201/09563

Abstract: A wiring board includes a first wiring layer, an insulating layer that is arranged on the first wiring layer, and a second wiring layer that is arranged on the insulating layer. The first wiring layer includes a first plain layer, an opening that penetrates through the first plain layer, and a reinforcing pad that is arranged in the opening. The second wiring layer includes a second plain layer. The insulating layer includes a reinforcing via that connects the reinforcing pad and the second plain layer.