公开(公告)号：US5079763A

公开(公告)日：1992-01-07

申请号：US662123

申请日：1991-02-28

申请人： Hung-Hsiang J. Chao ,  Gennady Shtirmer ,  Lanny S. Smoot

发明人： Hung-Hsiang J. Chao ,  Gennady Shtirmer ,  Lanny S. Smoot

IPC分类号： H04J3/06 ,  H04L12/28 ,  H04L12/56 ,  H04Q11/04

CPC分类号： H04L12/2852 ,  H04J3/0632 ,  H04Q11/0478 ,  H04L2012/5614

摘要： A method of controlling the access of a plurality of nodes to a bus which interconnects the nodes in a daisy chain. The method enables each node in the network to keep track of the transmission requests of all other nodes. Each node will compare it's needs against all requests and will only transmit onto the network after it has let pass sufficient resources to satisfy the downstream nodes.

摘要翻译： 控制多个节点对连接菊花链中的节点的总线的访问的方法。 该方法使得网络中的每个节点能够跟踪所有其他节点的传输请求。 每个节点将根据所有请求进行比较，只有在传递足够的资源以满足下游节点之后，才能将其传输到网络上。

公开(公告)号：US5278828A

公开(公告)日：1994-01-11

申请号：US893265

申请日：1992-06-04

申请人： Hung-Hsiang J. Chao

发明人： Hung-Hsiang J. Chao

IPC分类号： H04L12/56 ,  H04Q11/04 ,  H04J3/26

CPC分类号： H04L49/30 ,  H04L49/20 ,  H04L49/3081 ,  H04L49/508 ,  H04Q11/0478 ,  H04L2012/5651 ,  H04L2012/5672 ,  H04L2012/5681 ,  H04L49/103

摘要： A queue management method and system manages queued cells in such a way that higher priority cells are always served first, the low priority cells are dropped when the queue is full and, within the same priority, any interference is prevented. Four different architecture designs for such queue management are presented and their implementation feasibility and hardware complexity are compared and contrasted. A departure sequence is assigned to each cell in the novel architecture to implement the queue management. The sequence applies the concepts of fully distributed and highly parallel processing to schedule cell sending or dropping sequences. Preferably, a sequencer is provided such that the queue size and the number of priority levels can grow flexibly and without limit.

摘要翻译： 队列管理方法和系统以这样的方式管理排队的小区，使得始终首先服务较高优先级的小区，当队列满时，低优先级小区被丢弃，并且在相同的优先级内，防止任何干扰。 介绍了这种队列管理的四种不同架构设计，并对其实现可行性和硬件复杂性进行了比较和对比。 出发序列被分配给新颖架构中的每个小区以实现队列管理。 该序列应用完全分布和高度并行处理的概念来调度信元发送或丢弃序列。 优选地，提供定序器，使得队列大小和优先级数量可以灵活地且无限制地增长。

公开(公告)号：US5179552A

公开(公告)日：1993-01-12

申请号：US821264

申请日：1992-01-10

申请人： Hung-Hsiang J. Chao

发明人： Hung-Hsiang J. Chao

IPC分类号： H04J3/24 ,  H04L12/56 ,  H04Q11/04

CPC分类号： H04L12/5601 ,  H04J3/247 ,  H04L49/106 ,  H04L49/1553 ,  H04L49/1576 ,  H04L49/1584 ,  H04L49/258 ,  H04Q11/0478 ,  H04L2012/5627 ,  H04L2012/5647 ,  H04L2012/5651

摘要： A crosspoint matrix switching element and associated method for a large (e.g. approximately 1 Terabit/second) packet switch (200) or a non-buffer based statistical multiplexor (1810), using a crossbar matrix network in which, first, the output ports of individual switching elements (e.g. 1340.sub.1,1, 1340.sub.2,1) are partitioned into various groups (e.g. 1110) in order to share routing paths (links) (e.g. 1115.sub.1, 1115.sub.2, . . . , 1115.sub.K) among the elements in any such group and, second, the outputs of each such group are themselves recursively partitioned into a succession of serially connected groups (e.g. 1140, 1160) that each provides a decreasing number of outputs until one such output is provided for each corresponding output port (278.sub.1, 278.sub.2, . . . , 278.sub.N) of the switch. The switching element includes a control circuit which compares corresponding bits of two incoming bit streams in specific time windows to generate control signals and a routing circuit responsive to the control signals for routing the two input bit streams alternatively to two data outputs.

摘要翻译： 一种用于大（例如大约1兆位/秒）分组交换机（200）或非基于缓冲器的统计多路复用器（1810）的交叉点矩阵切换元件和相关方法，其使用交叉矩阵网络，其中，首先输出端口 各个开关元件（例如13401,1，13402,1）被划分成各种组（例如1110），以便在任何这样的组中的元件之间共享路由路径（链路）（例如，11151,11152，...，1115K） 并且其次，每个这样的组的输出本身被递归地划分成一系列串行连接的组（例如1140,1160），每个组提供递减数量的输出，直到为每个对应的输出端口提供一个这样的输出（2781,2782 ，...，278N）。 开关元件包括控制电路，其比较特定时间窗口中的两个输入比特流的相应比特以产生控制信号，以及响应于用于将两个输入比特流路由到两个数据输出的控制信号的路由电路。

公开(公告)号：US5381407A

公开(公告)日：1995-01-10

申请号：US893274

申请日：1992-06-04

申请人： Hung-Hsiang J. Chao

发明人： Hung-Hsiang J. Chao

IPC分类号： H04L12/56 ,  H04Q11/04 ,  H04J3/14

CPC分类号： H04L12/5602 ,  H04Q11/0478 ,  H04L2012/5636 ,  H04L2012/5637 ,  H04L2012/5651

摘要： A method and system are provided for controlling user traffic to a fast packet switching system using the leaky bucket scheme. Each of the packets (53 byte length cell) originates at a source of packets and has a virtual channel identifier (VCI). The method includes the step of receiving the packets, each of the packets having associated therewith an arrival time. The packets are stored at an addressable location in a first memory. The first memory having a plurality of addressable locations. In a second memory, there are stored addresses corresponding to the addressable locations in the first memory in which a packet is not yet stored. The addresses stored in the second memory are utilized in the step of storing the received packets. A credit manager circuit determines whether a stored packet complies with predetermined traffic parameters such as average arrival rate and maximum burst rate. This determination is based on a packet's arrival time and its VCI to obtain a validated packet. The credit manager circuit retrieves the validated packet from the first memory and the retrieved packet is then transmitted to the packet switching system.

摘要翻译： 提供了一种方法和系统，用于控制使用泄漏桶方案的快速分组交换系统的用户流量。 每个分组（53字节长度小区）起始于分组的源，并且具有虚拟信道标识符（VCI）。 该方法包括接收分组的步骤，每个分组具有相关联的到达时间。 分组被存储在第一存储器中的可寻址位置。 第一存储器具有多个可寻址位置。 在第二存储器中，存储对应于第一存储器中的可寻址位置的地址，其中分组尚未被存储。 存储在第二存储器中的地址在存储接收到的分组的步骤中被使用。 信用管理器电路确定存储的分组是否符合预定的业务参数，例如平均到达速率和最大突发速率。 该确定基于分组的到达时间和其VCI来获得经验证的分组。 信用管理电路从第一个存储器检索经过验证的数据包，然后将检索的数据包发送到数据包交换系统。

公开(公告)号：US5313579A

公开(公告)日：1994-05-17

申请号：US893266

申请日：1992-06-04

申请人： Hung-Hsiang J. Chao

发明人： Hung-Hsiang J. Chao

IPC分类号： H04L12/56 ,  H04Q11/04 ,  G06F13/00

CPC分类号： H04L12/5602 ,  H04Q11/0478 ,  H04L2012/5615 ,  H04L2012/5619 ,  H04L2012/5636 ,  H04L2012/5651 ,  H04L2012/5681

摘要： A sequencer chip device, provided for use in a broadband integrated service digital network (B-ISDN), is particularly adapted to control users' traffic at two places in the network: at the user-network interface (UNI) by a traffic enforcer, and at the network-node surface interface (NNI) by a queue manager. The traffic enforcer contains a buffer to delay and reshape violating cells that do not comply with some agreed-upon traffic parameters. The queue manager manages cells in a queue at network nodes in such a way that higher priority cells are always served first, low priority cells are discarded when the queue is full, and any interference between same-priority cells is prevented. Proposed architectures for the traffic enforcer and the queue manager include the chip device. The chip device includes a plurality of modules each of which is divided into three main functional areas: controller, memory and comparator. The chip device is preferably implemented using 1.2 .mu.m CMOS technology.

摘要翻译： 提供用于宽带综合业务数字网络（B-ISDN）的定序器芯片装置特别适用于在网络的两个地方控制用户的业务：在业务执行者的用户网络接口（UNI） 并在队列管理器的网络节点表面接口（NNI）上。 流量执行者包含一个缓冲区，用于延迟和重塑不符合某些商定的流量参数的违反细胞。 队列管理器在网络节点处管理队列中的小区，使得始终首先提供较高优先级的小区，当队列满时，丢弃低优先级小区，并且防止相同优先级小区之间的任何干扰。 流量执行者和队列管理器的建议架构包括芯片设备。 芯片装置包括多个模块，每个模块分为三个主要功能区域：控制器，存储器和比较器。 芯片器件优选使用1.2μmCMOS技术实现。

公开(公告)号：US5204882A

公开(公告)日：1993-04-20

申请号：US846769

申请日：1992-03-06

申请人： Hung-Hsiang J. Chao ,  Cesar A. Johnston

发明人： Hung-Hsiang J. Chao ,  Cesar A. Johnston

IPC分类号： H04J3/06 ,  H04L12/56 ,  H04Q11/04

CPC分类号： H04Q11/0478 ,  H04J3/0632 ,  H04L2012/5616 ,  H04L2012/5672

摘要： To recover the service clock of a variable bit rate source (170) which generates data at a rate which is not proportional to a service clock (76), timing cells are generated. The timing cells are generated at a rate which is proportional to the service clock (76). The timing cells and data are transmitted via a network (100). At the receive-end, the data is stored in a buffer (82). A phase locked loop (90') generates a local clock signal in the form of a read signal which controls the rate at which the received data is read out of the buffer (82). The read signal produced by the phase locked loop (90') is proportional to the average rate at which timing cells are received at the receive-end. In this manner the signal which reads the data out of the buffer (82) at the receive-end approaches the service clock (76) at the source end.

摘要翻译： 为了恢复以与服务时钟（76）不成比例的速率生成数据的可变比特率源（170）的服务时钟，产生定时单元。 定时单元以与服务时钟（76）成比例的速率产生。 定时单元和数据经由网络（100）发送。 在接收端，数据存储在缓冲器（82）中。 锁相环（90'）以读取信号的形式产生本地时钟信号，该读信号控制从缓冲器（82）读出接收数据的速率。 由锁相环（90'）产生的读信号与在接收端接收定时单元的平均速率成比例。 以这种方式，在接收端读取缓冲器（82）中的数据的信号在源端接近服务时钟（76）。

公开(公告)号：US5007070A

公开(公告)日：1991-04-09

申请号：US429840

申请日：1989-10-31

申请人： Hung-Hsiang J. Chao ,  Cesar A. Johnston

发明人： Hung-Hsiang J. Chao ,  Cesar A. Johnston

IPC分类号： H04J3/06

CPC分类号： H04J3/0632

摘要： A clock recovery circuit serves to recover a clock signal from data which does not arrive at predetermined times and which may be bursty. The clock recovery circuit operates in conjunction with a buffer which receives the data. Illustratively, the clock recovery circuit maintains a first count of the bytes of data written into the buffer and a second count of the byte of data transferred from the buffer. A subtractor substracts the second count from the first and a decision circuit utilizes the result to provide a signal indicative of the current occupancy of the buffer. Depending on the current occupancy, the frequency of an output signal of the clock recovery circuit is increased, decreased, or maintained as constant. This output signal thus serves as the recovered clock signal.

摘要翻译： 时钟恢复电路用于从不在预定时间到达并且可能是突发的数据恢复时钟信号。 时钟恢复电路与接收数据的缓冲器一起工作。 说明性地，时钟恢复电路维持写入缓冲器的数据的字节的第一计数，以及从缓冲器传送的数据的字节的第二计数。 减法器从第一计数器减去第二计数，并且判定电路利用结果来提供指示缓冲器的当前占用的信号。 根据当前占用率，时钟恢复电路的输出信号的频率增加，减小或维持为恒定。 因此，该输出信号用作恢复的时钟信号。

公开(公告)号：US4855999A

公开(公告)日：1989-08-08

申请号：US118979

申请日：1987-11-10

申请人： Hung-Hsiang J. Chao

发明人： Hung-Hsiang J. Chao

IPC分类号： H04J3/16 ,  H04J3/24 ,  H04L12/64

CPC分类号： H04L12/64 ,  H04J3/1682 ,  H04J3/247

摘要： A multiplexer for combining a plurality of relatively sparsely occupied DTDM bit streams into a smaller number of more densely occupied DTDM bit streams at the same bit rate is disclosed. The input lines of the multiplexer are divided into groups so that DTDM frames arriving on the input lines in one group are combined to form one outgoing DTDM bit stream. The outgoing DTDM bit streams are formed by synchronously generating chain of empty frames for each of the input line groups. The frames in a chain are passed to a first member of the appropriate input line group and by means of a cross-point switch to each succeeding member for the insertion of data. The groupings of input lines are defined by the settings of the cross-point switch and may be rearranged by changing the settings of the switch.

摘要翻译： 公开了一种多路复用器，用于将多个相对稀疏占用的DTDM比特流以相同比特率组合成较少数量的更密集占用的DTDM比特流。 复用器的输入线被分成组，使得到达一组中的输入线的DTDM帧被组合以形成一个输出的DTDM比特流。 输出的DTDM比特流通过为每个输入线路组同步产生空帧链来形成。 链中的帧被传递到适当输入线组的第一成员，并且通过交叉点切换传递给每个后续成员用于插入数据。 输入线的分组由交叉点开关的设置定义，可以通过更改开关的设置进行重新排列。

公开(公告)号：US5197064A

公开(公告)日：1993-03-23

申请号：US618119

申请日：1990-11-26

申请人： Hung-Hsiang J. Chao

发明人： Hung-Hsiang J. Chao

IPC分类号： H04J3/24 ,  H04L12/56 ,  H04Q11/04

CPC分类号： H04L12/5601 ,  H04J3/247 ,  H04L49/1576 ,  H04L49/1584 ,  H04L49/258 ,  H04Q11/0478 ,  H04L2012/5647 ,  H04L2012/5651 ,  H04L2012/5652 ,  H04L2012/5681

摘要： Apparatus, and accompanying methods for use therein, for illustratively implementing a large (e.g. approximately 1 Terabit/second) packet switch (200) or a non-buffer based statistical multiplexor (1810), using a crossbar matrix network in which, first, the output ports of individual switching elements (e.g. 1340.sub.1,1, 1340.sub.2,1) are partitioned into various groups (e.g. 1110) in order to share routing paths (links) (e.g. 1115.sub.1, 1115.sub.2, . . . , 1115.sub.K) among the elements in any such group and, second, the outputs of each such group are themselves recursively partitioned into a succession of serially connected groups (e.g. 1140, 1160) that each provides a decreasing number of outputs until one such output is provided for each corresponding output port (278.sub.1, 278.sub.2, . . . , 278.sub.N) of the switch. Such a switch also utilizes channel grouping to improve overall performance and a crossbar switching fabric that internally distributes contention resolution and filtering functions among the individual switching elements themselves to reduce complexity, provide modularity, reduce growth limitations and relax synchronization requirements of the entire switch.

摘要翻译： 装置及其使用的方法，用于示意性地使用交叉矩阵网络来实现大（例如大约1兆比特/秒）分组交换机（200）或非基于缓冲器的统计多路复用器（1810），其中，首先， 各个开关元件（例如，13401,1,13402,1）的输出端口被划分成各种组（例如，1110），以便共享各个元件之间的路由路径（链路）（例如，11151,11152，...，1115K） 任何这样的组，并且其次，每个这样的组的输出本身被递归地划分成一系列串行连接的组（例如1140,1160），每个组提供递减数量的输出，直到为每个对应的输出端口提供一个这样的输出（ 2781,2782，... 278N）。 这样的交换机还利用信道分组来提高总体性能，并且在各个交换单元本身内部分配争用解决和过滤功能的交叉交换结构以降低复杂性，提供模块化，减少增长限制并且放松整个交换机的同步要求。

公开(公告)号：US5124978A

公开(公告)日：1992-06-23

申请号：US637230

申请日：1991-01-03

申请人： Hung-Hsiang J. Chao

发明人： Hung-Hsiang J. Chao

IPC分类号： H04J3/24 ,  H04L12/56 ,  H04Q11/04

CPC分类号： H04L12/5601 ,  H04J3/247 ,  H04L49/1576 ,  H04L49/1584 ,  H04L49/258 ,  H04L49/455 ,  H04Q11/0478 ,  H04L2012/5647 ,  H04L2012/5651 ,  H04L2012/5674 ,  H04L2012/5681

摘要： Apparatus, and accompanying methods for use therein, for illustratively implementing a large (e.g. approximately 1 Terabit/second) packet switch (200) or a non-buffer based statistical multiplexor (1810), using a crossbar matrix network in which, first, the output ports of individual switching elements (e.g. 1340.sub.1,1, 1340.sub.2,1) are partitioned into various groups (e.g. 1110) in order to share routing paths (links) (e.g. 1115.sub.1, 1115.sub.2, . . . , 1115.sub.K) among the elements in any such group and, second, the outputs of each such group are themselves recursively partitioned into a succession of serially connected groups (e.g. 1140, 1160) that each provides a decreasing number of outputs until one such output is provided for each corresponding output port (278.sub.1, 278.sub.2, . . . , 278.sub.N) of the switch. Such a switch also utilizes channel grouping to improve overall performance and a crossbar switching fabric that internally distributes contention resolution and filtering functions among the individual switching elements themselves to reduce complexity, provide modularity, reduce growth limitations and relax synchronization requirements of the entire switch.

摘要翻译： 装置及其使用的方法，用于示意性地使用交叉矩阵网络来实现大（例如大约1兆比特/秒）分组交换机（200）或非基于缓冲器的统计多路复用器（1810），其中，首先， 各个开关元件（例如，13401,1,13402,1）的输出端口被划分成各种组（例如，1110），以便共享各个元件之间的路由路径（链路）（例如，11151,11152，...，1115K） 任何这样的组，并且其次，每个这样的组的输出本身被递归地划分成一系列串行连接的组（例如1140,1160），每个组提供递减数量的输出，直到为每个对应的输出端口提供一个这样的输出（ 2781,2782，... 278N）。 这样的交换机还利用信道分组来提高总体性能，并且在各个交换单元本身内部分配争用解决和过滤功能的交叉交换结构以降低复杂性，提供模块化，减少增长限制并且放松整个交换机的同步要求。