公开(公告)号：US07245158B2

公开(公告)日：2007-07-17

申请号：US11266544

申请日：2005-11-03

申请人： Hyang-Ja Yang ,  Ji-Suk Kwon ,  Hwa-Jin Kim

发明人： Hyang-Ja Yang ,  Ji-Suk Kwon ,  Hwa-Jin Kim

IPC分类号： G11C8/00 ,  G11C11/34

CPC分类号： G11C8/14 ,  H03K3/00 ,  H03K17/00

摘要： A circuit wiring layout in a semiconductor memory device comprises first and second p-type MOS transistors having channels connected to each other in series, and first and second n-type MOS transistors having sources connected in parallel to a drain of the second p-type MOS transistor, the p- and n-type MOS transistors forming a decoder NOR gating portion. The first and second n-type MOS transistors having drains connected to first and second main lines, respectively, and sources connected to a section line. The first and second p-type MOS transistors having gates to which select signals for first and second accesses are applied, respectively. The first and second p-type MOS transistors share an active junction with each other in a first area. The first and second n-type MOS transistors are spaced from the first area in a direction of the section line and have independent active junctions.

摘要翻译： 半导体存储器件中的电路布线布置包括具有彼此串联连接的沟道的第一和第二p型MOS晶体管，以及具有与第二p型漏极并联连接的源极的第一和第二n型MOS晶体管 MOS晶体管，形成解码器NOR门控部分的p型和n型MOS晶体管。 第一和第二n型MOS晶体管分别具有连接到第一和第二主线的漏极和连接到截面线的源极。 分别施加用于第一和第二访问的选择信号的第一和第二p型MOS晶体管。 第一和第二p型MOS晶体管在第一区域中共享彼此的有源结。 第一和第二n型MOS晶体管在截面线的方向上与第一区域间隔开并且具有独立的有源结。

公开(公告)号：US20060114030A1

公开(公告)日：2006-06-01

申请号：US11266544

申请日：2005-11-03

申请人： Hyang-Ja Yang ,  Ji-Suk Kwon ,  Hwa-Jin Kim

发明人： Hyang-Ja Yang ,  Ji-Suk Kwon ,  Hwa-Jin Kim

IPC分类号： H03K19/00

CPC分类号： G11C8/14 ,  H03K3/00 ,  H03K17/00

摘要： A circuit wiring layout in a semiconductor memory device comprises first and second p-type MOS transistors having channels connected to each other in series, and first and second n-type MOS transistors having sources connected in parallel to a drain of the second p-type MOS transistor, the p- and n-type MOS transistors forming a decoder NOR gating portion. The first and second n-type MOS transistors having drains connected to first and second main lines, respectively, and sources connected to a section line. The first and second p-type MOS transistors having gates to which select signals for first and second accesses are applied, respectively. The first and second p-type MOS transistors share an active junction with each other in a first area. The first and second n-type MOS transistors are spaced from the first area in a direction of the section line and have independent active junctions.

摘要翻译： 半导体存储器件中的电路布线布置包括具有彼此串联连接的沟道的第一和第二p型MOS晶体管，以及具有与第二p型漏极并联连接的源极的第一和第二n型MOS晶体管 MOS晶体管，形成解码器NOR门控部分的p型和n型MOS晶体管。 第一和第二n型MOS晶体管分别具有连接到第一和第二主线的漏极和连接到截面线的源极。 分别施加用于第一和第二访问的选择信号的第一和第二p型MOS晶体管。 第一和第二p型MOS晶体管在第一区域中共享彼此的有源结。 第一和第二n型MOS晶体管在截面线的方向上与第一区域间隔开并且具有独立的有源结。

公开(公告)号：US20050151561A1

公开(公告)日：2005-07-14

申请号：US11031723

申请日：2005-01-07

申请人： Myung-Han Choi ,  Hwa-Jin Kim ,  Young-Dae Lee

发明人： Myung-Han Choi ,  Hwa-Jin Kim ,  Young-Dae Lee

IPC分类号： G11C7/10 ,  H03K19/003

CPC分类号： H03K19/00384

摘要： There is provided an output driver for use in a semiconductor device capable of remarkably improving linearity of impedance by reducing or minimizing a change of an impedance for output data caused due to a change of an external power supply. The output driver for outputting internal data of a semiconductor device to the exterior of a chip comprises a first driving section including a driving transistor to maintain an impedance for applied data at a certain level in response to the data; and a second driving section for compensating for linearity of the impedance in response to an operation signal from the driving transistor of the first driving section and providing an output terminal with the data.

摘要翻译： 提供了一种用于半导体器件的输出驱动器，其能够通过减少或最小化由于外部电源的变化引起的输出数据的阻抗的变化来显着提高阻抗的线性。 用于将半导体器件的内部数据输出到芯片外部的输出驱动器包括：第一驱动部分，其包括驱动晶体管，以响应于该数据将应用数据的阻抗保持在一定水平; 以及第二驱动部分，用于响应于来自第一驱动部分的驱动晶体管的操作信号补偿阻抗的线性，并向输出端提供数据。

公开(公告)号：US20130062102A1

公开(公告)日：2013-03-14

申请号：US13697246

申请日：2010-07-19

申请人： Sung Won Lee ,  Jae Beum Kim ,  Hwa Jin Kim

发明人： Sung Won Lee ,  Jae Beum Kim ,  Hwa Jin Kim

IPC分类号： H05K1/03 ,  H05K3/06

CPC分类号： H05K3/427 ,  H05K1/0393 ,  H05K3/108 ,  H05K2201/0154

摘要： The present invention relates to a double-sided flexible printed circuit board in which circuit patterns are formed, including an insulating substrate, conduction layers sputtered on both sides of the insulating substrate, a through hole formed to connect circuits formed in the both sides, seed layers formed on the conduction layers of the both sides, and pattern plating layers formed on an inner wall of the through hole and on the respective seed layers, and a method of manufacturing the same. Accordingly, the loss of a circuit width can be minimized because a sputtering-type material not an adhesive is used between the insulating substrate and the thin copper (Cu) layer. Further, productivity can be improved because a roll-to-roll process can be used. In addition, the thickness of a circuit can be controlled and micro circuit patterns can be formed because a semi-additive method is used.

摘要翻译： 本发明涉及一种双面柔性印刷电路板，其中形成有电路图案，包括绝缘基板，溅射在绝缘基板的两侧的导电层，形成为连接形成在两侧的电路的通孔，种子 形成在两侧的导电层上的层以及形成在通孔的内壁上和各个种子层上的图案镀层及其制造方法。 因此，在绝缘基板和薄铜（Cu）层之间使用不是粘合剂的溅射型材料，可以使电路宽度的损失最小化。 此外，可以提高生产率，因为可以使用卷对卷工艺。 此外，可以控制电路的厚度，并且可以形成微电路图案，因为使用半添加方法。

公开(公告)号：US07292068B2

公开(公告)日：2007-11-06

申请号：US11031723

申请日：2005-01-07

申请人： Myung-Han Choi ,  Hwa-Jin Kim ,  Young-Dae Lee

发明人： Myung-Han Choi ,  Hwa-Jin Kim ,  Young-Dae Lee

IPC分类号： H03K19/0175

CPC分类号： H03K19/00384

摘要： There is provided an output driver for use in a semiconductor device capable of remarkably improving linearity of impedance by reducing or minimizing a change of an impedance for output data caused due to a change of an external power supply. The output driver for outputting internal data of a semiconductor device to the exterior of a chip comprises a first driving section including a driving transistor to maintain an impedance for applied data at a certain level in response to the data; and a second driving section for compensating for linearity of the impedance in response to an operation signal from the driving transistor of the first driving section and providing an output terminal with the data.

摘要翻译： 提供了一种用于半导体器件的输出驱动器，其能够通过减少或最小化由于外部电源的变化引起的输出数据的阻抗的变化来显着提高阻抗的线性。 用于将半导体器件的内部数据输出到芯片外部的输出驱动器包括：第一驱动部分，其包括驱动晶体管，以响应于该数据将应用数据的阻抗保持在一定水平; 以及第二驱动部分，用于响应于来自第一驱动部分的驱动晶体管的操作信号补偿阻抗的线性，并向输出端提供数据。