公开(公告)号：US08266080B2

公开(公告)日：2012-09-11

申请号：US12354356

申请日：2009-01-15

申请人： Won-Hyouk Jang ,  Joo-Hwa Lee ,  Dong-Hyun Kim ,  Hyo-Jin Han ,  Kil-Ho Ok ,  Sung-Hoon Kim

发明人： Won-Hyouk Jang ,  Joo-Hwa Lee ,  Dong-Hyun Kim ,  Hyo-Jin Han ,  Kil-Ho Ok ,  Sung-Hoon Kim

IPC分类号： G06F15/18

CPC分类号： G01B11/0641 ,  G01B11/0683 ,  H01L22/12 ,  H01L22/20

摘要： A virtual measuring device and a method for measuring the deposition thickness of amorphous silicon being deposited on a substrate is disclosed, where the method of measuring the deposition thickness of amorphous silicon includes predicting and adapting operations. In the predicting operation, during a process of depositing the amorphous silicon to a substrate, the deposition thickness is predicted by multiplying a predicted deposition speed to a deposition time by using a prediction model expressing a relationship between a deposition speed and a plurality of process factors that are correlated with the deposition speed obtained from the deposition thickness and the deposition time, and the predicted deposition thickness is compared with the measured deposition thickness, so that the relationship between the plurality of process factors and the deposition speed in the prediction model is compensated according to the comparison difference.

摘要翻译： 公开了一种用于测量沉积在衬底上的非晶硅的沉积厚度的虚拟测量装置和方法，其中测量非晶硅的沉积厚度的方法包括预测和适应操作。 在预测操作中，在将非晶硅沉积到衬底的过程中，通过使用表示沉积速度和多个工艺因素之间的关系的预测模型将预测的沉积速度乘以沉积时间来预测沉积厚度 与从沉积厚度和沉积时间获得的沉积速度相关联，并将预测的沉积厚度与测量的沉积厚度进行比较，使得多个工艺因素之间的关系和预测模型中的沉积速度被补偿 根据比较差异。

公开(公告)号：US20090307163A1

公开(公告)日：2009-12-10

申请号：US12354356

申请日：2009-01-15

申请人： Won-Hyouk JANG ,  Joo-Hwa Lee ,  Dong-Hyun Kim ,  Hyo-Jin Han ,  Kil-Ho Ok ,  Sung-Hoon Kim

发明人： Won-Hyouk JANG ,  Joo-Hwa Lee ,  Dong-Hyun Kim ,  Hyo-Jin Han ,  Kil-Ho Ok ,  Sung-Hoon Kim

IPC分类号： G06F15/18 ,  H01L21/66 ,  G01B21/08 ,  G06N5/02 ,  G06F17/10

CPC分类号： G01B11/0641 ,  G01B11/0683 ,  H01L22/12 ,  H01L22/20

摘要： A virtual measuring device and a method for measuring the deposition thickness of amorphous silicon being deposited on a substrate is disclosed, where the method of measuring the deposition thickness of amorphous silicon includes predicting and adapting operations. In the predicting operation, during a process of depositing the amorphous silicon to a substrate, the deposition thickness is predicted by multiplying a predicted deposition speed to a deposition time by using a prediction model expressing a relationship between a deposition speed and a plurality of process factors that are correlated with the deposition speed obtained from the deposition thickness and the deposition time, and the predicted deposition thickness is compared with the measured deposition thickness, so that the relationship between the plurality of process factors and the deposition speed in the prediction model is compensated according to the comparison difference.

摘要翻译： 公开了一种用于测量沉积在衬底上的非晶硅的沉积厚度的虚拟测量装置和方法，其中测量非晶硅的沉积厚度的方法包括预测和适应操作。 在预测操作中，在将非晶硅沉积到衬底的过程中，通过使用表示沉积速度和多个工艺因素之间的关系的预测模型将预测的沉积速度乘以沉积时间来预测沉积厚度 与从沉积厚度和沉积时间获得的沉积速度相关联，并将预测的沉积厚度与测量的沉积厚度进行比较，使得多个工艺因素之间的关系和预测模型中的沉积速度被补偿 根据比较差异。

公开(公告)号：US5151874A

公开(公告)日：1992-09-29

申请号：US617813

申请日：1990-11-26

申请人： Ho-sun Jeong ,  Hyo-jin Han

发明人： Ho-sun Jeong ,  Hyo-jin Han

IPC分类号： G06F7/552

CPC分类号： G06F7/5525 ,  G06F2207/4802

摘要： An integrated circuit for performing a square root operation uses adders made in accordance with neural network concepts. The integrated circuit includes an exponent part, a first mantissa part, a second mantissa part and a control part. The exponent part computes an exponent of the square root of an input operand; the first mantissa part preprocesses the mantissa of the input operand; the second mantissa part computes the square root of the output from the first mantissa part; and the control part controls interaction of input and output among various components of the integrated circuits. Because the adders used in integrated circuit are composed of neural network circuits having a short propagation time for carry bits, the integrated circuit can computer a square root fast and efficiently.

摘要翻译： 用于执行平方根操作的集成电路使用根据神经网络概念制作的加法器。 集成电路包括指数部分，第一尾数部分，第二尾数部分和控制部分。 指数部分计算输入操作数的平方根的指数; 第一尾数部分预处理输入操作数的尾数; 第二尾数部分计算第一尾数部分的输出的平方根; 并且控制部分控制集成电路的各个部件之间的输入和输出的相互作用。 由于集成电路中使用的加法器由进位位传播时间短的神经网络电路组成，所以集成电路可以快速，高效地计算平方根。

公开(公告)号：US5347613A

公开(公告)日：1994-09-13

申请号：US745346

申请日：1991-08-15

申请人： Ho-sun Chung ,  Hyo-jin Han

发明人： Ho-sun Chung ,  Hyo-jin Han

IPC分类号： G06F15/18 ,  G06G7/60 ,  G06N3/04 ,  G06N3/063 ,  G06N99/00 ,  G11C11/54 ,  H01L21/822 ,  H01L27/04

CPC分类号： G06K9/4604 ,  G06N3/063

摘要： Disclosed is a multi-layer neural network and circuit design method. The multi-layer neural network receiving an m-bit input and generating an n-bit output comprises a neuron having a cascaded pair of CMOS inverters and having an output node of the preceding CMOS inverter among the pair of CMOS inverters as its inverted output node and an output node of the succeeding CMOS inverter as its non-inverted output node, an input layer having m neurons to receive the m-bit input, an output layer having n neurons to generate the n-bit output, at least one hidden layer provided with n neurons to transfer the input received from the input layer to every upper hidden layer and the output layer, an input synapse group in a matrix having each predetermined weight value to connect each output of neurons on the input layer to each neuron of the output layer and at least one hidden layer, at least one transfer synapse group in a matrix having each predetermined weight value to connect each output of neurons of the hidden layer to each neuron of every upper hidden layer and the output layer, and a bias synapse group for biasing each input node of neurons of the hidden layers and the output layer.

摘要翻译： 公开了一种多层神经网络和电路设计方法。 接收m位输入并生成n位输出的多层神经网络包括具有级联的CMOS反相器对的神经元，并且在一对CMOS反相器之间具有前述CMOS反相器的输出节点作为其反相输出节点 以及后续CMOS反相器的输出节点作为其非反相输出节点，具有m个神经元以接收m位输入的输入层，具有n个神经元以产生n位输出的输出层，至少一个隐藏层 提供有n个神经元以将从输入层接收的输入传送到每个上隐层和输出层，矩阵中的输入突触组具有每个预定权重值，以将输入层上的神经元的每个输出连接到 输出层和至少一个隐藏层，具有每个预定权重值的矩阵中的至少一个转移突触组，以将隐藏层的神经元的每个输出连接到每个上隐层的每个神经元 和输出层，以及偏置突触组，用于偏置隐藏层和输出层的神经元的每个输入节点。