利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

6 条记录 (耗时 0.058 秒)

    Display substrate and method of manufacturing the same
    1.
    发明授权
    Display substrate and method of manufacturing the same 有权
    显示基板及其制造方法

    公开(公告)号：US08779429B2

    公开(公告)日：2014-07-15

    申请号：US13565639

    申请日：2012-08-02

    申请人： O-Sung Seo ,  Hwa-Yeul Oh ,  Hyoung-Cheol Lee ,  Tae-Kyung Yim

    发明人： O-Sung Seo ,  Hwa-Yeul Oh ,  Hyoung-Cheol Lee ,  Tae-Kyung Yim

    IPC分类号： H01L27/14 ,  H01L21/84

    CPC分类号： H01L27/124 ,  H01L27/3272 ,  H01L27/3279 ,  H01L29/78633

    摘要： RC delay in gate lines of a wide display is reduced by using a low resistivity conductor in the gate lines and a different conductor for forming corresponding gate electrodes. More specifically, a corresponding display substrate includes a gate line made of a first gate line metal, a data line made of a first data line metal, a pixel transistor and a first connection providing part. The pixel transistor includes a first active pattern formed of polycrystalline silicon (poly-Si) and a first gate electrode formed there above and made of a conductive material different from the first gate line metal. The first connection providing part connects the first gate electrode to the gate line. On the other hand, the source electrode is integrally extended from the data line.

    摘要翻译： 通过在栅极线中使用低电阻率导体和用于形成对应的栅电极的不同导体来减小宽显示器的栅极线中的RC延迟。 更具体地，对应的显示基板包括由第一栅极线金属制成的栅极线，由第一数据线金属制成的数据线，像素晶体管和第一连接提供部。 像素晶体管包括由多晶硅（poly-Si）形成的第一有源图案和形成在其上方并由不同于第一栅极线金属的导电材料制成的第一栅电极。 第一连接提供部分将第一栅电极连接到栅极线。 另一方面，源电极从数据线整体延伸。

    ARRAY SUBSTRATE AND METHOD OF FABRICATING THE SAME
    3.
    发明申请
    ARRAY SUBSTRATE AND METHOD OF FABRICATING THE SAME 有权
    阵列基板及其制造方法

    公开(公告)号：US20130256668A1

    公开(公告)日：2013-10-03

    申请号：US13599945

    申请日：2012-08-30

    申请人： Hwa Yeul OH ,  Osung SEO ,  Jeanho SONG ,  Hyoung Cheol LEE ,  Taekyung YIM

    发明人： Hwa Yeul OH ,  Osung SEO ,  Jeanho SONG ,  Hyoung Cheol LEE ,  Taekyung YIM

    IPC分类号： H01L29/786 ,  H01L33/02

    CPC分类号： H01L29/66757 ,  H01L29/78633

    摘要： Provided is an array substrate including a base substrate, a thin film transistor having a semiconductor layer disposed on a first part of the base substrate. The semiconductor layer includes a source electrode and a drain electrode, a gate electrode disposed on the semiconductor layer and insulated from the semiconductor layer. A light-blocking layer disposed between the base substrate and the thin film transistor. The light-blocking layer comprises a first layer continuously disposed on and around the first part of the base substrate, and a second layer formed on the first part of the base substrate without extending outside of the first part, the second layer being disposed on the first layer.

    摘要翻译： 提供了一种阵列基板，包括基底基板，薄膜晶体管，其具有设置在基底基板的第一部分上的半导体层。 半导体层包括源电极和漏电极，设置在半导体层上并与半导体层绝缘的栅电极。 设置在基底基板和薄膜晶体管之间的遮光层。 遮光层包括连续地设置在基底基板的第一部分上和周围的第一层，以及形成在基底基板的第一部分上而不延伸到第一部分外侧的第二层，第二层设置在第一层上 第一层

    DISPLAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME
    4.
    发明申请
    DISPLAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME 有权
    显示基板及其制造方法

    公开(公告)号：US20130234144A1

    公开(公告)日：2013-09-12

    申请号：US13565639

    申请日：2012-08-02

    申请人： O-Sung SEO ,  Hwa-Yeul OH ,  Hyoung-Cheol LEE ,  Tae-Kyung YIM

    发明人： O-Sung SEO ,  Hwa-Yeul OH ,  Hyoung-Cheol LEE ,  Tae-Kyung YIM

    IPC分类号： H01L27/15 ,  H01L33/08

    CPC分类号： H01L27/124 ,  H01L27/3272 ,  H01L27/3279 ,  H01L29/78633

    摘要： RC delay in gate lines of a wide display is reduced by using a low resistivity conductor in the gate lines and a different conductor for forming corresponding gate electrodes. More specifically, a corresponding display substrate includes a gate line made of a first gate line metal, a data line made of a first data line metal, a pixel transistor and a first connection providing part. The pixel transistor includes a first active pattern formed of polycrystalline silicon (poly-Si) and a first gate electrode formed there above and made of a conductive material different from the first gate line metal. The first connection providing part connects the first gate electrode to the gate line. On the other hand, the source electrode is integrally extended from the data line.

    摘要翻译： 通过在栅极线中使用低电阻率导体和用于形成对应的栅电极的不同导体来减小宽显示器的栅极线中的RC延迟。 更具体地，对应的显示基板包括由第一栅极线金属制成的栅极线，由第一数据线金属制成的数据线，像素晶体管和第一连接提供部。 像素晶体管包括由多晶硅（poly-Si）形成的第一有源图案和形成在其上方并由不同于第一栅极线金属的导电材料制成的第一栅电极。 第一连接提供部分将第一栅电极连接到栅极线。 另一方面，源电极从数据线整体延伸。

    Array substrate and method of fabricating the same
    5.
    发明授权
    Array substrate and method of fabricating the same 有权
    阵列基板及其制造方法

    公开(公告)号：US09024323B2

    公开(公告)日：2015-05-05

    申请号：US13599945

    申请日：2012-08-30

    申请人： Hwa Yeul Oh ,  Osung Seo ,  Jeanho Song ,  Hyoung Cheol Lee ,  Taekyung Yim

    发明人： Hwa Yeul Oh ,  Osung Seo ,  Jeanho Song ,  Hyoung Cheol Lee ,  Taekyung Yim

    IPC分类号： H01L29/04 ,  H01L29/66 ,  H01L29/786

    CPC分类号： H01L29/66757 ,  H01L29/78633

    摘要： Provided is an array substrate including a base substrate, a thin film transistor having a semiconductor layer disposed on a first part of the base substrate. The semiconductor layer includes a source electrode and a drain electrode, a gate electrode disposed on the semiconductor layer and insulated from the semiconductor layer. A light-blocking layer disposed between the base substrate and the thin film transistor. The light-blocking layer comprises a first layer continuously disposed on and around the first part of the base substrate, and a second layer formed on the first part of the base substrate without extending outside of the first part, the second layer being disposed on the first layer.

    摘要翻译： 提供了一种阵列基板，包括基底基板，薄膜晶体管，其具有设置在基底基板的第一部分上的半导体层。 半导体层包括源电极和漏电极，设置在半导体层上并与半导体层绝缘的栅电极。 设置在基底基板和薄膜晶体管之间的遮光层。 遮光层包括连续地设置在基底基板的第一部分上和周围的第一层，以及形成在基底基板的第一部分上而不延伸到第一部分外侧的第二层，第二层设置在第一层上 第一层