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    THIN FILM TRANSISTOR STRUCTURE
    2.
    发明公开
    THIN FILM TRANSISTOR STRUCTURE 审中-公开

    公开(公告)号：US20240014277A1

    公开(公告)日：2024-01-11

    申请号：US18323424

    申请日：2023-05-25

    申请人： E Ink Holdings Inc.

    发明人： Ming-Kai CHUANG ,  Lih-Hsiung CHAN

    IPC分类号： H01L29/417 ,  H01L29/423 ,  H01L29/786

    CPC分类号： H01L29/41733 ,  H01L29/42384 ,  H01L29/78663

    摘要： A thin film transistor structure includes a gate electrode, a gate insulation layer, a first amorphous silicon layer, a source/drain electrode, and a second amorphous silicon layer. The gate insulation layer is located on the gate electrode. The first amorphous silicon layer is located on the gate insulation layer. The source/drain electrode is located on the first amorphous silicon layer. The second amorphous silicon layer is located in the gate insulation layer.

    Process for preparing a channel region of a thin-film transistor in a 3-dimensional thin-film transistor array
    3.
    发明授权
    Process for preparing a channel region of a thin-film transistor in a 3-dimensional thin-film transistor array 有权

    公开(公告)号：US11844204B2

    公开(公告)日：2023-12-12

    申请号：US18050937

    申请日：2022-10-28

    申请人： SUNRISE MEMORY CORPORATION

    发明人： Vinod Purayath ,  Jie Zhou ,  Wu-Yi Henry Chien ,  Eli Harari

    IPC分类号： H01L29/66 ,  H10B99/00 ,  H01L29/786 ,  H01L21/3065

    CPC分类号： H10B99/00 ,  H01L21/3065 ,  H01L29/6675 ,  H01L29/78642 ,  H01L29/78663 ,  H01L29/78672

    摘要： A process includes (a) providing a semiconductor substrate having a planar surface; (b) forming a plurality of thin-film layers above the planar surface of the semiconductor substrate, one on top of another, including among the thin-film layers first and second isolation layers, wherein a significantly greater concentration of a first dopant specie is provided in the first isolation layer than in the second isolation layer; (c) etching along a direction substantially orthogonal to the planar surface through the thin-films to create a trench having sidewalls that expose the thin-film layers; (d) depositing conformally a semiconductor material on the sidewalls of the trench; (e) annealing the first isolation layer at a predetermined temperature and a predetermined duration such that the first isolation layer act as a source of the first dopant specie which dopes a portion of the semiconductor material adjacent the first isolation layer; and (f) selectively etching the semiconductor material to remove the doped portion of the semiconductor material without removing the remainder of the semiconductor material.