公开(公告)号：US12007429B2

公开(公告)日：2024-06-11

申请号：US17848972

申请日：2022-06-24

Applicant: IC ANALYTICA, LLC

Inventor： Patrick G. Drennan ,  Joseph S. Spector ,  Richard Wunderlich

IPC: G01R31/27 ,  G01R1/073 ,  G01R31/26

CPC classification number: G01R31/275 ,  G01R1/07342 ,  G01R31/2601

Abstract: An apparatus has a semiconductor wafer hosting rows and columns of chips, where the rows and columns of chips are separated by scribe lines. Voltage regulators are positioned within the scribe lines. Each voltage regulator is connected to one or more chips. Selection circuitry is positioned within the scribe lines. The selection circuitry governs access to a chip being tested.

公开(公告)号：US20220413037A1

公开(公告)日：2022-12-29

申请号：US17848972

申请日：2022-06-24

Applicant: IC ANALYTICA, LLC

Inventor： Patrick G. DRENNAN ,  Joseph S. SPECTOR ,  Richard WUNDERLICH

IPC: G01R31/27 ,  G01R1/073 ,  G01R31/26

Abstract: An apparatus has a semiconductor wafer hosting rows and columns of chips, where the rows and columns of chips are separated by scribe lines. Voltage regulators are positioned within the scribe lines. Each voltage regulator is connected to one or more chips. Selection circuitry is positioned within the scribe lines. The selection circuitry governs access to a chip being tested.

公开(公告)号：US20220413040A1

公开(公告)日：2022-12-29

申请号：US17849008

申请日：2022-06-24

Applicant: IC ANALYTICA, LLC

Inventor： Patrick G. DRENNAN ,  Joseph S. SPECTOR ,  Richard WUNDERLICH

IPC: G01R31/28 ,  G01R1/073

Abstract: An apparatus has a semiconductor wafer hosting rows and columns of chips, where the rows and columns of chips are separated by scribe lines. Vertical and horizontal routing lines are in the scribe lines interconnecting the rows and columns of chips. Test circuit sites are in the scribe lines, each test circuit site including contact pads for simultaneous connection to probe card needles, sensor circuit select and control circuitry, and a sensor circuit bank.

公开(公告)号：US12153087B2

公开(公告)日：2024-11-26

申请号：US17849008

申请日：2022-06-24

Applicant: IC ANALYTICA, LLC

Inventor： Patrick G. Drennan ,  Joseph S. Spector ,  Richard Wunderlich

IPC: G01R31/28 ,  G01R1/02 ,  G01R1/04 ,  G01R1/067 ,  G01R1/073 ,  G01R31/26

Abstract: An apparatus has a semiconductor wafer hosting rows and columns of chips, where the rows and columns of chips are separated by scribe lines. Vertical and horizontal routing lines are in the scribe lines interconnecting the rows and columns of chips. Test circuit sites are in the scribe lines, each test circuit site including contact pads for simultaneous connection to probe card needles, sensor circuit select and control circuitry, and a sensor circuit bank.

公开(公告)号：US20220415728A1

公开(公告)日：2022-12-29

申请号：US17848991

申请日：2022-06-24

Applicant: IC ANALYTICA, LLC

Inventor： Patrick G. DRENNAN ,  Joseph S. SPECTOR ,  Richard WUNDERLICH

IPC: H01L21/66 ,  G01R31/28

Abstract: An apparatus has a semiconductor wafer hosting rows and columns of chips, where the rows and columns of chips are separated by scribe lines. There are test circuit sites in the scribe lines, each test circuit site including contact pads for simultaneous connection to probe card needles, sensor circuit select and control circuitry, and a sensor circuit bank.

公开(公告)号：US20220415727A1

公开(公告)日：2022-12-29

申请号：US17848954

申请日：2022-06-24

Applicant: IC ANALYTICA, LLC

Inventor： Joseph S. SPECTOR ,  Richard WUNDERLICH ,  Patrick G. DRENNAN

IPC: H01L21/66 ,  G01R31/28

Abstract: An apparatus has a semiconductor wafer hosting rows and columns of chips, where the rows and columns of chips are separated by scribe lines. Selection circuitry is positioned within the scribe lines. The selection circuitry is connected to test circuits in the scribe lines. The selection circuitry operates to enable voltage control at a single test circuit while disabling all other test circuits.

公开(公告)号：US20220413045A1

公开(公告)日：2022-12-29

申请号：US17848934

申请日：2022-06-24

Applicant: IC ANALYTICA, LLC

Inventor： Richard WUNDERLICH ,  Joseph S. SPECTOR ,  Brian DEGNAN ,  Patrick G. DRENNAN

IPC: G01R31/317 ,  G01R31/3185

Abstract: An apparatus has a collection of ring oscillators. An instruction register block is configured to sequentially address and activate each ring oscillator in the collection of ring oscillators. A multiplexer with input lines is connected to each ring oscillator in the collection of ring oscillators and an output line. A pulse counter is connected to the output line of the multiplexer to count the number of oscillations of a selected ring oscillator within a selected time period to form a multiple bit frequency count output signal. A data shift register receives the multiple bit frequency count output signal and produces a serial frequency count output signal.