公开(公告)号：US20110202713A1

公开(公告)日：2011-08-18

申请号：US13049487

申请日：2011-03-16

申请人： Ian Mes

发明人： Ian Mes

IPC分类号： G06F12/00

CPC分类号： G11C7/1072 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076

摘要： An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous signal is used to latch data at every stage. The asynchronous control signals are generated within the chip and are optimized to the different latency stages. Longer latency stages require larger delays elements, while shorter latency states require shorter delay elements. The data is synchronized to the clock at the end of the read data path before being read out of the chip. Because the data has been latched at each pipeline stage, it suffers from less skew than would be seen in a conventional wave pipeline architecture. Furthermore, since the stages are independent of the system clock, the read data path can be run at any CAS latency as long as the re-synchronizing output is built to support it.

摘要翻译： 异步流水线SDRAM具有由异步信号控制的单独流水线级。 不是使用时钟信号在每个阶段同步数据，而是使用异步信号来锁存每个阶段的数据。 异步控制信号在芯片内产生，并针对不同的延迟级进行了优化。 更长的延迟阶段需要更大的延迟元件，而较短的等待时间状态需要更短的延迟元件。 在从芯片读出之前，数据与读取数据路径末端的时钟同步。 由于数据已经在每个流水线阶段被锁存，所以它比在传统的波浪管线架构中看到的偏差更小。 此外，由于这些阶段与系统时钟无关，只要构建重新同步输出以支持读取数据路径，就可以以任何CAS延迟运行。

公开(公告)号：US07865685B2

公开(公告)日：2011-01-04

申请号：US12371255

申请日：2009-02-13

申请人： Ian Mes

发明人： Ian Mes

IPC分类号： G06F12/00

CPC分类号： G11C7/1072 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076

摘要： An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous signal is used to latch data at every stage. The asynchronous control signals are generated within the chip and are optimized to the different latency stages. Longer latency stages require larger delays elements, while shorter latency states require shorter delay elements. The data is synchronized to the clock at the end of the read data path before being read out of the chip. Because the data has been latched at each pipeline stage, it suffers from less skew than would be seen in a conventional wave pipeline architecture. Furthermore, since the stages are independent of the system clock, the read data path can be run at any CAS latency as long as the re-synchronizing output is built to support it.

公开(公告)号：US20080062975A1

公开(公告)日：2008-03-13

申请号：US11517465

申请日：2006-09-08

申请人： Ian Mes ,  Ian Dublin ,  Christian Bourget

发明人： Ian Mes ,  Ian Dublin ,  Christian Bourget

IPC分类号： H04L12/56

CPC分类号： G06F13/385 ,  H04M11/062

摘要： A system and method for optimizing the transmission of signals over a group of wires. In a preferred form of the present invention, a multi-wire bus connects a common card to a plurality of line cards. A framing protocol controls transmissions between the common card and the plurality of line cards. The framing protocol includes a frame having a prefix that identifies in which direction a given transmission will occur. The prefix also identifies over which wire or wires a given line card will receive data. Each of the line cards are configured to interpret the prefix so that at any given time data can be transmitted from the common card to one or more of the line cards by either transmission over a single wire or a plurality of wires.

摘要翻译： 一种用于优化一组电线上的信号传输的系统和方法。 在本发明的优选形式中，多线总线将公共卡连接到多个线卡。 成帧协议控制公共卡和多个线卡之间的传输。 成帧协议包括具有前缀的帧，其标识在哪个方向上发生给定的传输。 该前缀还标识给定线卡将接收数据的电线或电线。 每个线路卡被配置为解释前缀，使得在任何给定时间，可以通过单线或多条线路的传输将数据从普通卡发送到一个或多个线路卡。

公开(公告)号：US06539454B2

公开(公告)日：2003-03-25

申请号：US09129878

申请日：1998-08-06

申请人： Ian Mes

发明人： Ian Mes

IPC分类号： G06F1200

CPC分类号： G11C7/106 ,  G11C7/1039 ,  G11C7/1051

摘要： An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous signal is used to latch data at every stage. The asynchronous control signals are generated within the chip and are optimized to the different latency stages. Longer latency stages require larger delays elements, while shorter latency states require shorter delay elements. The data is synchronized to the clock at the end of the read data path before being read out of the chip. Because the data has been latched at each pipeline stage, it suffers from less skew than would be seen in a conventional wave pipeline architecture. Furthermore, since the stages are independent of the system clock, the read data path can be run at any CAS latency as long as the re-synchronizing output is built to support it.

公开(公告)号：US08601231B2

公开(公告)日：2013-12-03

申请号：US13327154

申请日：2011-12-15

申请人： Ian Mes

发明人： Ian Mes

IPC分类号： G06F12/00 ,  G06F1/12 ,  G06F1/00 ,  G11C8/00 ,  G11C8/16

CPC分类号： G11C7/1072 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076

摘要： An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous signal is used to latch data at every stage. The asynchronous control signals are generated within the chip and are optimized to the different latency stages. Longer latency stages require larger delays elements, while shorter latency states require shorter delay elements. The data is synchronized to the clock at the end of the read data path before being read out of the chip. Because the data has been latched at each pipeline stage, it suffers from less skew than would be seen in a conventional wave pipeline architecture. Furthermore, since the stages are independent of the system clock, the read data path can be run at any CAS latency as long as the re-synchronizing output is built to support it.

公开(公告)号：US07274738B2

公开(公告)日：2007-09-25

申请号：US10386910

申请日：2003-03-11

申请人： Ian Mes

发明人： Ian Mes

IPC分类号： H04B1/66

CPC分类号： H03M7/30 ,  G06F9/3001

摘要： In a telecommunications system, an arithmetic logic unit (ALU) that receives an input signal. The input signal includes a digital signal representative of an analog signal. The ALU selectively performs compression and decompression on the digital signal. The ALU comprises the following elements. A standard ALU component performs standard ALU operations on the input signal. An encoding unit selectively performs compression on the digital signal. A decoding unit selectively performs decompression on the digital signal. An instruction decoder receives and decodes an ALU instruction. An output selector selects a result from one of the standard ALU component, the encoding unit, and the decoding unit in accordance with the decoded instruction and provides the result as an output.

摘要翻译： 在电信系统中，接收输入信号的算术逻辑单元（ALU）。 输入信号包括表示模拟信号的数字信号。 ALU选择性地对数字信号进行压缩和解压缩。 ALU包括以下元件。 标准ALU组件对输入信号执行标准ALU操作。 编码单元选择性地对数字信号进行压缩。 解码单元选择性地对数字信号进行解压缩。 指令解码器接收并解码ALU指令。 输出选择器根据解码指令从标准ALU组件，编码单元和解码单元之一中选择一个结果，并将结果作为输出。

公开(公告)号：US20120144131A1

公开(公告)日：2012-06-07

申请号：US13327154

申请日：2011-12-15

申请人： Ian Mes

发明人： Ian Mes

IPC分类号： G06F12/00

CPC分类号： G11C7/1072 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076

摘要： An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous signal is used to latch data at every stage. The asynchronous control signals are generated within the chip and are optimized to the different latency stages. Longer latency stages require larger delays elements, while shorter latency states require shorter delay elements. The data is synchronized to the clock at the end of the read data path before being read out of the chip. Because the data has been latched at each pipeline stage, it suffers from less skew than would be seen in a conventional wave pipeline architecture. Furthermore, since the stages are independent of the system clock, the read data path can be run at any CAS latency as long as the re-synchronizing output is built to support it.

摘要翻译： 异步流水线SDRAM具有由异步信号控制的单独流水线级。 不是使用时钟信号在每个阶段同步数据，而是使用异步信号来锁存每个阶段的数据。 异步控制信号在芯片内产生，并针对不同的延迟级进行了优化。 更长的延迟阶段需要更大的延迟元件，而较短的等待时间状态需要更短的延迟元件。 在从芯片读出之前，数据与读取数据路径末端的时钟同步。 由于数据已经在每个流水线阶段被锁存，所以它比在传统的波浪管线架构中看到的偏差更小。 此外，由于这些阶段与系统时钟无关，只要构建重新同步输出以支持读取数据路径，就可以以任何CAS延迟运行。

公开(公告)号：US08078821B2

公开(公告)日：2011-12-13

申请号：US12773531

申请日：2010-05-04

申请人： Ian Mes

发明人： Ian Mes

IPC分类号： G06F12/00 ,  G06F1/12 ,  G06F1/00 ,  G11C8/00 ,  G11C8/16 ,  G11C8/18 ,  G11C7/00

CPC分类号： G11C7/1072 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076

摘要： An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous signal is used to latch data at every stage. The asynchronous control signals are generated within the chip and are optimized to the different latency stages. Longer latency stages require larger delays elements, while shorter latency states require shorter delay elements. The data is synchronized to the clock at the end of the read data path before being read out of the chip. Because the data has been latched at each pipeline stage, it suffers from less skew than would be seen in a conventional wave pipeline architecture. Furthermore, since the stages are independent of the system clock, the read data path can be run at any CAS latency as long as the re-synchronizing output is built to support it.

摘要翻译： 异步流水线SDRAM具有由异步信号控制的单独流水线级。 不是使用时钟信号在每个阶段同步数据，而是使用异步信号来锁存每个阶段的数据。 异步控制信号在芯片内产生，并针对不同的延迟级进行了优化。 更长的延迟阶段需要更大的延迟元件，而较短的等待时间状态需要更短的延迟元件。 在从芯片读出之前，数据与读取数据路径末端的时钟同步。 由于数据已经在每个流水线阶段被锁存，所以它比在传统的波浪管线架构中看到的偏差更小。 此外，由于这些阶段与系统时钟无关，只要构建重新同步输出以支持读取数据路径，就可以以任何CAS延迟运行。

公开(公告)号：US07509469B2

公开(公告)日：2009-03-24

申请号：US11673834

申请日：2007-02-12

申请人： Ian Mes

发明人： Ian Mes

IPC分类号： G06F12/00 ,  G06F1/12 ,  G11C8/18 ,  G11C8/00

CPC分类号： G11C7/1072 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076

摘要： An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous signal is used to latch data at every stage. The asynchronous control signals are generated within the chip and are optimized to the different latency stages. Longer latency stages require larger delays elements, while shorter latency states require shorter delay elements. The data is synchronized to the clock at the end of the read data path before being read out of the chip. Because the data has been latched at each pipeline stage, it suffers from less skew than would be seen in a conventional wave pipeline architecture. Furthermore, since the stages are independent of the system clock, the read data path can be run at any CAS latency as long as the re-synchronizing output is built to support it.

摘要翻译： 异步流水线SDRAM具有由异步信号控制的单独流水线级。 不是使用时钟信号在每个阶段同步数据，而是使用异步信号来锁存每个阶段的数据。 异步控制信号在芯片内产生，并针对不同的延迟级进行了优化。 更长的延迟阶段需要更大的延迟元件，而较短的等待时间状态需要更短的延迟元件。 在从芯片读出之前，数据与读取数据路径末端的时钟同步。 由于数据已经在每个流水线阶段被锁存，所以它比在传统的波浪管线架构中看到的偏差更小。 此外，由于这些阶段与系统时钟无关，只要构建重新同步输出来支持读取数据路径，就可以以任何CAS延迟运行。

公开(公告)号：US08122218B2

公开(公告)日：2012-02-21

申请号：US13049487

申请日：2011-03-16

申请人： Ian Mes

发明人： Ian Mes

IPC分类号： G06F12/00 ,  G06F1/12 ,  G06F1/00 ,  G11C8/00 ,  G11C8/16 ,  G11C8/18 ,  G11C7/00

CPC分类号： G11C7/1072 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076

摘要： An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous signal is used to latch data at every stage. The asynchronous control signals are generated within the chip and are optimized to the different latency stages. Longer latency stages require larger delays elements, while shorter latency states require shorter delay elements. The data is synchronized to the clock at the end of the read data path before being read out of the chip. Because the data has been latched at each pipeline stage, it suffers from less skew than would be seen in a conventional wave pipeline architecture. Furthermore, since the stages are independent of the system clock, the read data path can be run at any CAS latency as long as the re-synchronizing output is built to support it.

摘要翻译： 异步流水线SDRAM具有由异步信号控制的单独流水线级。 不是使用时钟信号在每个阶段同步数据，而是使用异步信号来锁存每个阶段的数据。 异步控制信号在芯片内产生，并针对不同的延迟级进行了优化。 更长的延迟阶段需要更大的延迟元件，而较短的等待时间状态需要更短的延迟元件。 在从芯片读出之前，数据与读取数据路径末端的时钟同步。 因为数据已经在每个流水线阶段被锁存，所以它比在传统的波形管线架构中看到的偏差更小。 此外，由于这些阶段与系统时钟无关，只要构建重新同步输出来支持读取数据路径，就可以以任何CAS延迟运行。