公开(公告)号：US08093128B2

公开(公告)日：2012-01-10

申请号：US12125864

申请日：2008-05-22

申请人： William W. C. Koutny, Jr. ,  Sam Geha ,  Igor Kouznetsov ,  Krishnaswamy Ramkumar ,  Fredrick B. Jenne ,  Sagy Levy ,  Ravindra Kapre ,  Jeremy Warren

发明人： William W. C. Koutny, Jr. ,  Sam Geha ,  Igor Kouznetsov ,  Krishnaswamy Ramkumar ,  Fredrick B. Jenne ,  Sagy Levy ,  Ravindra Kapre ,  Jeremy Warren

IPC分类号： H01L29/792

CPC分类号： H01L29/7833 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7836 ,  H01L29/7843

摘要： A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels of the logic device. HF pre-cleans and SC1 cleans may be avoided to improve the quality of a blocking layer of the non-volatile charge trap memory device. The blocking layer may be thermally reoxidized or nitridized during a thermal oxidation or nitridation of a logic MOS gate insulator layer to densify the blocking layer. A multi-layered liner may be utilized to first offset a source and drain implant in a high voltage logic device and also block silicidation of the nonvolatile charge trap memory device.

公开(公告)号：US20080293207A1

公开(公告)日：2008-11-27

申请号：US12125864

申请日：2008-05-22

申请人： William W.C. Koutny, JR. ,  Sam Geha ,  Igor Kouznetsov ,  Krishnaswamy Ramkumar ,  Fredrick B. Jenne ,  Sagy Levy ,  Ravindra Kapre ,  Jeremy Warren

发明人： William W.C. Koutny, JR. ,  Sam Geha ,  Igor Kouznetsov ,  Krishnaswamy Ramkumar ,  Fredrick B. Jenne ,  Sagy Levy ,  Ravindra Kapre ,  Jeremy Warren

IPC分类号： H01L21/336

CPC分类号： H01L29/7833 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7836 ,  H01L29/7843

摘要： A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels of the logic device. HF pre-cleans and SC1 cleans may be avoided to improve the quality of a blocking layer of the non-volatile charge trap memory device. The blocking layer may be thermally reoxidized or nitridized during a thermal oxidation or nitridation of a logic MOS gate insulator layer to densify the blocking layer. A multi-layered liner may be utilized to first offset a source and drain implant in a high voltage logic device and also block silicidation of the nonvolatile charge trap memory device.

摘要翻译： 一种半导体结构及其形成方法。 半导体结构包括具有设置在第一区域上的非易失性电荷陷阱存储器件和设置在第二区域上的逻辑器件的衬底。 可以在形成逻辑器件的阱和通道之后形成电荷陷阱电介质叠层。 可以避免HF预清洗和SC1清洁，以提高非挥发性电荷陷阱存储器件的阻挡层的质量。 在逻辑MOS栅极绝缘体层的热氧化或氮化期间，阻挡层可以被热再氧化或氮化，以致密封阻挡层。 可以使用多层衬垫来首先在高压逻辑器件中偏置源极和漏极注入，并且还阻挡非易失性电荷陷阱存储器件的硅化。

公开(公告)号：US06531366B1

公开(公告)日：2003-03-11

申请号：US09904328

申请日：2001-07-12

申请人： Igor Kouznetsov

发明人： Igor Kouznetsov

IPC分类号： H01L21336

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11546 ,  H01L29/66575

摘要： A method of fabricating a semiconductor device (300) is disclosed. A low energy ion implantation (318) may form low voltage source and drain regions in a low voltage region (402-3) of a substrate. A low energy implant may also form a portion of source and drain regions in a high voltage region (402-2). A high energy ion implantation (322) may complete the formation of high voltage transistors in a high voltage region (402-2). A high voltage gate structure (418-2) may be exposed during a high energy ion implantation and mask a channel region.

摘要翻译： 公开了制造半导体器件（300）的方法。 低能离子注入（318）可以在衬底的低电压区域（402-3）中形成低电压源极和漏极区域。 低能量注入还可以在高电压区域（402-2）中形成源区和漏区的一部分。 高能离子注入（322）可以在高电压区域（402-2）中完成高电压晶体管的形成。 高电压栅极结构（418-2）可以在高能量离子注入期间暴露并且掩蔽沟道区域。