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    Nitridation oxidation of tunneling layer for improved SONOS speed and retention
    3.
    发明申请
    Nitridation oxidation of tunneling layer for improved SONOS speed and retention 有权
    隧道层的氮化氧化提高了SONOS的速度和保留时间

    公开(公告)号：US20090032863A1

    公开(公告)日：2009-02-05

    申请号：US12005813

    申请日：2007-12-27

    申请人： Sagy Levy ,  Krishnaswamy Ramkumar ,  Fredrick B. Jenne

    发明人： Sagy Levy ,  Krishnaswamy Ramkumar ,  Fredrick B. Jenne

    IPC分类号： H01L29/792 ,  H01L21/336

    CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L21/3143 ,  H01L29/4234 ,  H01L29/4916 ,  H01L29/512 ,  H01L29/513 ,  H01L29/518

    摘要： A method for forming a tunneling layer of a nonvolatile trapped-charge memory device and the article made thereby. The method includes multiple oxidation and nitridation operations to provide a dielectric constant higher than that of a pure silicon dioxide tunneling layer but with a fewer hydrogen and nitrogen traps than a tunneling layer having nitrogen at the substrate interface. The method provides for an improved memory window in a SONOS-type device. In one embodiment, the method includes an oxidation, a nitridation, a reoxidation and a renitridation. In one implementation, the first oxidation is performed with O2 and the reoxidation is performed with NO.

    摘要翻译： 一种用于形成非易失性俘获电荷存储装置的隧道层的方法及其制成的制品。 该方法包括多次氧化和氮化操作，以提供比纯二氧化硅隧道层更高的介电常数，但是具有比在衬底界面处具有氮的隧穿层更少的氢和氮阱。 该方法提供了SONOS型设备中改进的存储器窗口。 在一个实施方案中，该方法包括氧化，氮化，再氧化和重新染色。 在一个实施方案中，首先用O 2进行氧化，并用NO进行再氧化。

    Integration of non-volatile charge trap memory devices and logic CMOS devices
    5.
    发明授权
    Integration of non-volatile charge trap memory devices and logic CMOS devices 有权
    集成非易失性电荷陷阱存储器件和逻辑CMOS器件

    公开(公告)号：US08679927B2

    公开(公告)日：2014-03-25

    申请号：US12185751

    申请日：2008-08-04

    申请人： Krishnaswamy Ramkumar ,  Fredrick B. Jenne ,  Sagy Levy

    发明人： Krishnaswamy Ramkumar ,  Fredrick B. Jenne ,  Sagy Levy

    IPC分类号： H01L29/792

    CPC分类号： H01L29/7833 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7836 ,  H01L29/7843

    摘要： A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels of the logic device. HF pre-cleans and SC1 cleans may be avoided to improve the quality of a blocking layer of the non-volatile charge trap memory device. The blocking layer may be thermally reoxidized or nitridized during a thermal oxidation or nitridation of a logic MOS gate insulator layer to densify the blocking layer. A multi-layered liner may be utilized to first offset a source and drain implant in a high voltage logic device and also block silicidation of the nonvolatile charge trap memory device.

    摘要翻译： 一种半导体结构及其形成方法。 半导体结构包括具有设置在第一区域上的非易失性电荷陷阱存储器件和设置在第二区域上的逻辑器件的衬底。 可以在形成逻辑器件的阱和通道之后形成电荷陷阱电介质叠层。 可以避免HF预清洗和SC1清洁，以提高非挥发性电荷陷阱存储器件的阻挡层的质量。 在逻辑MOS栅极绝缘体层的热氧化或氮化期间，阻挡层可以被热再氧化或氮化，以致密封阻挡层。 可以使用多层衬垫来首先在高压逻辑器件中偏置源极和漏极注入，并且还阻挡非易失性电荷陷阱存储器件的硅化。

    Nitridation oxidation of tunneling layer for improved SONOS speed and retention
    7.
    发明授权
    Nitridation oxidation of tunneling layer for improved SONOS speed and retention 有权
    隧道层的氮化氧化提高了SONOS的速度和保留时间

    公开(公告)号：US08637921B2

    公开(公告)日：2014-01-28

    申请号：US12005813

    申请日：2007-12-27

    申请人： Sagy Levy ,  Krishnaswamy Ramkumar ,  Fredrick B. Jenne

    发明人： Sagy Levy ,  Krishnaswamy Ramkumar ,  Fredrick B. Jenne

    IPC分类号： H01L29/792

    CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L21/3143 ,  H01L29/4234 ,  H01L29/4916 ,  H01L29/512 ,  H01L29/513 ,  H01L29/518

    摘要： A method for forming a tunneling layer of a nonvolatile trapped-charge memory device and the article made thereby. The method includes multiple oxidation and nitridation operations to provide a dielectric constant higher than that of a pure silicon dioxide tunneling layer but with a fewer hydrogen and nitrogen traps than a tunneling layer having nitrogen at the substrate interface. The method provides for an improved memory window in a SONOS-type device. In one embodiment, the method includes an oxidation, a nitridation, a reoxidation and a renitridation. In one implementation, the first oxidation is performed with O2 and the reoxidation is performed with NO.

    摘要翻译： 一种用于形成非易失性俘获电荷存储装置的隧道层的方法及其制成的制品。 该方法包括多次氧化和氮化操作，以提供比纯二氧化硅隧道层更高的介电常数，但是具有比在衬底界面处具有氮的隧穿层更少的氢和氮阱。 该方法提供了SONOS型设备中改进的存储器窗口。 在一个实施方案中，所述方法包括氧化，氮化，再氧化和再纳入。 在一个实施方案中，首先用O 2进行氧化，并用NO进行再氧化。

    Oxide-nitride-oxide stack having multiple oxynitride layers
    9.
    发明授权
    Oxide-nitride-oxide stack having multiple oxynitride layers 有权
    具有多个氮氧化物层的氧化物 - 氮化物 - 氧化物堆叠

    公开(公告)号：US08643124B2

    公开(公告)日：2014-02-04

    申请号：US13007533

    申请日：2011-01-14

    申请人： Sagy Levy ,  Krishnaswamy Ramkumar ,  Fredrick Jenne ,  Sam Geha

    发明人： Sagy Levy ,  Krishnaswamy Ramkumar ,  Fredrick Jenne ,  Sam Geha

    IPC分类号： H01L21/336

    CPC分类号： H01L29/512 ,  C23C16/0272 ,  C23C16/308 ,  G11C16/0466 ,  H01L21/0214 ,  H01L21/02271 ,  H01L21/28282 ,  H01L21/3145 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/792

    摘要： A semiconductor device including a silicon-oxide-oxynitride-oxide-silicon structure and methods of forming the same are provided. Generally, the structure comprises: a tunnel oxide layer on a surface of a substrate including silicon; a multi-layer charge storing layer including an oxygen-rich, first oxynitride layer on the tunnel oxide layer in which the stoichiometric composition of the first oxynitride layer results in it being substantially trap free, and an oxygen-lean, second oxynitride layer on the first oxynitride layer in which the stoichiometric composition of the second oxynitride layer results in it being trap dense; a blocking oxide layer on the second oxynitride layer; and a silicon containing gate layer on the blocking oxide layer. Other embodiments are also disclosed.

    摘要翻译： 提供了包括氧化硅 - 氧氮化物 - 氧化物 - 硅结构的半导体器件及其形成方法。 通常，该结构包括：在包括硅的衬底的表面上的隧道氧化物层; 多层电荷存储层，其包括在所述隧道氧化物层上的富氧第一氧氮化物层，其中所述第一氧氮化物层的化学计量组成导致其基本上不含杂质，并且所述第二氧氮化物层 第一氮氧化物层，其中第二氮氧化物层的化学计量组成导致其陷阱致密; 在第二氮氧化物层上的阻挡氧化物层; 以及在所述阻挡氧化物层上的含硅栅极层。 还公开了其他实施例。

    OXIDE-NITRIDE-OXIDE STACK HAVING MULTIPLE OXYNITRIDE LAYERS
    10.
    发明申请
    OXIDE-NITRIDE-OXIDE STACK HAVING MULTIPLE OXYNITRIDE LAYERS 有权
    具有多个氧化物层的氧化物 - 氮氧化物堆

    公开(公告)号：US20130175504A1

    公开(公告)日：2013-07-11

    申请号：US13436872

    申请日：2012-03-31

    申请人： Sagy Levy ,  Krishnaswamy Ramkumar ,  Fredrick Jenne ,  Sam Geha

    发明人： Sagy Levy ,  Krishnaswamy Ramkumar ,  Fredrick Jenne ,  Sam Geha

    IPC分类号： H01L29/775

    CPC分类号： H01L29/66833 ,  B82Y10/00 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/14 ,  H01L21/28282 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/4234 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/7833 ,  H01L29/792 ,  H01L29/7926

    摘要： An embodiment of a semiconductor memory device including a multi-layer charge storing layer and methods of forming the same are described. Generally, the device includes a channel formed from a semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide layer overlying the channel; and a multi-layer charge storing layer including an oxygen-rich, first oxynitride layer on the tunnel oxide layer in which a stoichiometric composition of the first oxynitride layer results in it being substantially trap free, and an oxygen-lean, second oxynitride layer on the first oxynitride layer in which a stoichiometric composition of the second oxynitride layer results in it being trap dense. In one embodiment, the device comprises a non-planar transistor including a gate having multiple surfaces abutting the channel, and the gate comprises the tunnel oxide layer and the multi-layer charge storing layer.

    摘要翻译： 描述了包括多层电荷存储层的半导体存储器件的实施例及其形成方法。 通常，该器件包括由半导体材料形成的沟道，该半导体材料覆盖连接存储器件的源极和漏极的衬底上的表面; 覆盖通道的隧道氧化物层; 以及多层电荷存储层，其在所述隧道氧化物层上包含富氧的第一氧氮化物层，其中所述第一氧氮化物层的化学计量组成导致其基本上无陷阱，并且将贫氧的第二氮氧化物层置于 第一氧氮化物层，其中第二氧氮化物层的化学计量组成导致其陷阱致密。 在一个实施例中，该器件包括非平面晶体管，其包括具有邻接通道的多个表面的栅极，并且栅极包括隧道氧化物层和多层电荷存储层。