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    Open drain driver having enhanced immunity to I/O ground noise
    1.
    发明授权
    Open drain driver having enhanced immunity to I/O ground noise 有权

    公开(公告)号：US06472906B2

    公开(公告)日：2002-10-29

    申请号：US09749704

    申请日：2000-12-27

    申请人： Ikuo Jimmy Sanwo ,  Mahyar Nejat ,  Jean-Robert Clerge

    发明人： Ikuo Jimmy Sanwo ,  Mahyar Nejat ,  Jean-Robert Clerge

    IPC分类号： H03K190175

    CPC分类号： H03K17/162 ,  H03K19/00361

    摘要： An open drain I/O driver includes an input node, an output node, a first reference node, a first transistor, and noise immunity circuitry. The first transistor has its gate coupled to the input node and its conducting path coupled in series with the output node and the first reference node. The first transistor operates to uncouple the output node from the first reference node in response to an input voltage applied to the input node. The noise immunity circuitry keeps the output node uncoupled from the first reference node during undershoot noise in a first reference voltage that causes the first transistor to change from an off state to an on state. The noise immunity circuitry includes second and third transistors. The second transistor has its gate coupled to the input node and its conducting path coupled in series with the conducting path of the first transistor. The third transistor is configured to keep the second transistor in an off state during the undershoot noise.

    Apparatus and method of providing a programmable slew rate control output driver
    3.
    发明授权
    Apparatus and method of providing a programmable slew rate control output driver 失效
    提供可编程转换速率控制输出驱动器的装置和方法

    公开(公告)号：US5977790A

    公开(公告)日：1999-11-02

    申请号：US884438

    申请日：1997-06-27

    申请人： Ikuo Jimmy Sanwo ,  Mahyar Nejat ,  Hiroshi Takano

    发明人： Ikuo Jimmy Sanwo ,  Mahyar Nejat ,  Hiroshi Takano

    IPC分类号： H03K19/0175 ,  H03K19/003 ,  H03K19/0185

    CPC分类号： H03K19/00361

    摘要： The present invention is a method and apparatus for providing slew rate control. The apparatus comprises a first circuit and a second circuit having an output terminal that is coupled to a first end of the first circuit. The second circuit receives a first input signal and a second input signal. The apparatus further comprises a third circuit having an output terminal that is coupled to the first end of the first circuit. The third circuit also receives the first input signal and the second input signal. The first circuit generates an output signal having a predetermined slew rate, where the output signal has a first state when the first and second input signals are in a first state.

    摘要翻译： 本发明是提供转换速率控制的方法和装置。 该装置包括第一电路和第二电路，其具有耦合到第一电路的第一端的输出端。 第二电路接收第一输入信号和第二输入信号。 该装置还包括具有耦合到第一电路的第一端的输出端的第三电路。 第三电路还接收第一输入信号和第二输入信号。 第一电路产生具有预定转换速率的输出信号，其中当第一和第二输入信号处于第一状态时，输出信号具有第一状态。

    High speed CMOS bus transmitter and receiver
    4.
    发明授权
    High speed CMOS bus transmitter and receiver 失效
    高速CMOS总线发送器和接收器

    公开(公告)号：US5903167A

    公开(公告)日：1999-05-11

    申请号：US812961

    申请日：1997-03-05

    申请人： Ikuo Jimmy Sanwo ,  Paul Georgief

    发明人： Ikuo Jimmy Sanwo ,  Paul Georgief

    IPC分类号： G06F3/00 ,  H03K19/017 ,  H03K19/0175 ,  H03K19/0185 ,  H04L25/02

    CPC分类号： H03K19/01707 ,  H03K19/018592

    摘要： A circuit, system, and method for increasing the speed of a bus by reducing the capacitive loading effect of transistors coupled to the bus are provided. The transistors, which are sub-micrometer channel length CMOS transistors, make up a tranceiver comprised of a transmitter and a reciever. The transistors that make up the transciever are coupled to the bus through a pair of Schottky diodes in series. The diode pair is coupled to isolate the bus from the junction capacitance of the transistors. The bus is a multi-segment transmission line with a characteristic impedance. The opposite ends of the transmission line are terminated with the characteristic impedance of the transmission line. The voltage swing of the bus is limited to approximately 1 volt. The pair of Schottky diodes isolate the signal bus line from the capacitive loading effects of the transistor drivers used to drive the voltages on the transmitting end of the bus, especially when the bus is being pulled to a logic high level. This results in minimal loading of the bus line and allows for a faster transmission rate. Speed is also increased by having only approximately a 1 volt swing of the bus line between logic high and logic low voltage states. All devices for this circuit can be fabricated using a standard metal-oxide-semiconductor fabrication process.

    摘要翻译： 提供了一种通过降低耦合到总线的晶体管的电容负载效应来提高总线速度的电路，系统和方法。 作为亚微米通道长度CMOS晶体管的晶体管构成由发射器和接收器组成的收发器。 构成转码器的晶体管通过串联的一对肖特基二极管耦合到总线。 二极管对被耦合以将总线与晶体管的结电容隔离。 总线是具有特征阻抗的多段传输线。 传输线的相对端用传输线的特性阻抗终止。 总线的电压摆幅限制在大约1伏。 这对肖特基二极管将信号总线与用于驱动总线发送端的电压的晶体管驱动器的电容负载效应隔离，特别是当总线被拉至逻辑高电平时。 这导致总线线路的最小负载，并允许更快的传输速率。 通过在逻辑高电平和逻辑低电压状态之间只有大约1伏的总线摆幅来提高速度。 该电路的所有器件可以使用标准的金属氧化物半导体制造工艺制造。