公开(公告)号：US11224376B2

公开(公告)日：2022-01-18

申请号：US13976395

申请日：2011-04-29

Applicant: Myung Whan Suh ,  Il Yong Park ,  Seung Ha Oh ,  Chung Ku Rhee ,  Phil Sang Chung

Inventor： Myung Whan Suh ,  Il Yong Park ,  Seung Ha Oh ,  Chung Ku Rhee ,  Phil Sang Chung

IPC: A61B5/12 ,  A61B5/374 ,  A61B5/38 ,  A61B5/316

Abstract: The tinnitus testing apparatus of this invention comprises a control part that in turn comprises: an auditory stimulus generation part that can generate a stimulus; and an AEP acquisition and amplitude measurement part that can acquire auditory evoked potential (AEP) brain waves of a examinee due to said stimulus and measure the specific amplitude of said acquired brainwaves; wherein said auditory stimulus is one or more of: a 1st stimulus containing continuous noise and pulse noise; and a 2nd stimulus containing pulse noise and continuous noise with a silent gap.

公开(公告)号：USD676608S1

公开(公告)日：2013-02-19

申请号：US29420335

申请日：2012-05-08

Applicant: Il-Yong Park

Designer： Il-Yong Park

公开(公告)号：US08067289B2

公开(公告)日：2011-11-29

申请号：US12629543

申请日：2009-12-02

Applicant: Il-Yong Park

Inventor： Il-Yong Park

IPC: H01L21/336

CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/7838

Abstract: A semiconductor device and a method of manufacturing a semiconductor device. A semiconductor device may include an epitaxial layer over a semiconductor substrate, a first well region over a epitaxial layer, a first isolation layer and/or a third isolation layer at opposite sides of said first well region and/or a second isolation layer over a first well region between first and third isolation layers. A semiconductor device may include a gate over a second isolation layer. A semiconductor device may include a second well region over a first well region between a third isolation layer and a gate, a first ion-implanted region over a second well region between a third isolation layer and a gate, and/or a second ion-implanted region between a first ion-implanted region and a gate. A semiconductor device may include an accumulation channel between a second well region and a gate.

Abstract translation: 半导体器件和半导体器件的制造方法。 半导体器件可以包括在半导体衬底上的外延层，外延层上的第一阱区，在所述第一阱区的相对侧的第一隔离层和/或第三隔离层和/或第一隔离层 第一和第三隔离层之间的第一阱区。 半导体器件可以包括在第二隔离层上的栅极。 半导体器件可以包括在第三隔离层和栅极之间的第一阱区域上的第二阱区域，在第三隔离层和栅极之间的第二阱区域上的第一离子注入区域和/或第二离子注入区域， 注入区域在第一离子注入区域和栅极之间。 半导体器件可以包括在第二阱区域和栅极之间的累积通道。

公开(公告)号：US20090281367A1

公开(公告)日：2009-11-12

申请号：US12261510

申请日：2008-10-30

Applicant: Jin-Ho Cho ,  Il-Yong Park ,  Sang-Heun Lee ,  Kyu-yup Lee ,  Myoung-Nam Kim ,  Ki-Woong Seong

Inventor： Jin-Ho Cho ,  Il-Yong Park ,  Sang-Heun Lee ,  Kyu-yup Lee ,  Myoung-Nam Kim ,  Ki-Woong Seong

IPC: H04R25/00

CPC classification number: H04R25/606

Abstract: A trans-tympanic membrane transducer and an implantable hearing aid system using the same. The trans-tympanic membrane transducer vibrates the tympanic membrane using a miniature magnetic member perpendicularly extending through a portion of the tympanic membrane and a coil implanted adjacent to the magnet to generate alternating magnetic field corresponding to sound signal, so as to remarkably improve sound qualities in high frequency bands, which are hardly achievable by a conventional air conduction hearing aid. This overcomes difficulty, inconvenience and risk associated with a conventional operation that implants a miniature magnet on the surface of the tympanic membrane or on an auditory organ such as the ossicle in the middle ear.

Abstract translation: 透鼓膜换能器和使用其的可植入助听器系统。 透鼓膜传感器使用垂直延伸穿过鼓膜的一部分的微型磁性构件和与磁体相邻地植入的线圈振动鼓膜，以产生对应于声音信号的交变磁场，从而显着提高声音质量 高频带，这是常规的空气传导助听器难以实现的。 这克服了在鼓膜表面或听觉器官如中耳中的小骨上植入微型磁体的常规操作的难度，不便和风险。

公开(公告)号：US07391393B2

公开(公告)日：2008-06-24

申请号：US10739735

申请日：2003-12-17

Applicant: Yil-Suk Yang ,  Byung-Doo Kim ,  Jong-Dae Kim ,  Tae-Moon Roh ,  Dae-Woo Lee ,  Byoung-Gon Yu ,  Il-Yong Park ,  Sung-ku Kwon

Inventor： Yil-Suk Yang ,  Byung-Doo Kim ,  Jong-Dae Kim ,  Tae-Moon Roh ,  Dae-Woo Lee ,  Byoung-Gon Yu ,  Il-Yong Park ,  Sung-ku Kwon

IPC: G09G3/30

CPC classification number: G09G3/3283 ,  G09G3/3241 ,  G09G2310/027 ,  G09G2330/021

Abstract: Disclosed is a low power and high density source driver and a current driven active matrix organic electroluminescent device having the same, in which all elements operate at a normal voltage and all circuits of the source driver are shielded from a high voltage of a panel. The source driver includes: a shift register for generating an enable signal for storing data; a data latch circuit for storing digital data inputted from an exterior; a line latch circuit for sequentially storing the data in response to the enable signal and outputting the stored data in parallel at one time in response to a load signal; a current type digital-to-analog converter for converting the digital data outputted from the line latch circuit into an analog signal, the analog signal being outputted in a form of a current signal; and a high voltage shield circuit for transferring the output of the current digital-to-analog converter to source lines of an external panel and for shielding internal circuits from a high voltage of the panel. The shift register, the data latch circuit, the line latch circuit, the current type digital-to-analog converter and the high voltage shield circuit are driven at a normal voltage.

Abstract translation: 公开了一种低功率和高密度源极驱动器以及具有这种驱动器的电流驱动有源矩阵有机电致发光器件，其中所有元件都工作在正常电压，并且源极驱动器的所有电路都屏蔽了面板的高电压。 源极驱动器包括：移位寄存器，用于产生用于存储数据的使能信号; 数据锁存电路，用于存储从外部输入的数字数据; 行锁存电路，用于响应于使能信号顺序地存储数据并响应于负载信号一次并行地输出存储的数据; 用于将从线路锁存电路输出的数字数据转换为模拟信号的电流型数模转换器，模拟信号以电流信号的形式输出; 以及用于将当前数模转换器的输出传送到外部面板的源极线并用于屏蔽内部电路与面板的高电压的高压屏蔽电路。 移位寄存器，数据锁存电路，线路锁存电路，电流型数模转换器和高压屏蔽电路以正常电压驱动。

公开(公告)号：USD561398S1

公开(公告)日：2008-02-05

申请号：US29289374

申请日：2007-07-18

Applicant: Il-Yong Park

Designer： Il-Yong Park

公开(公告)号：US06852597B2

公开(公告)日：2005-02-08

申请号：US10071127

申请日：2002-02-08

Applicant: Il-Yong Park ,  Jong Dae Kim ,  Sang Gi Kim ,  Jin Gun Koo ,  Dae Woo Lee ,  Roh Tae Moon ,  Yang Yil Suk

Inventor： Il-Yong Park ,  Jong Dae Kim ,  Sang Gi Kim ,  Jin Gun Koo ,  Dae Woo Lee ,  Roh Tae Moon ,  Yang Yil Suk

IPC: H01L21/336 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/7813 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/7802

Abstract: A method for fabricating a power semiconductor device having a trench gate structure is provided. An epitaxial layer of a first conductivity type having a low concentration and a body region of a second conductivity type are sequentially formed on a semiconductor substrate of the first conductivity type having a high concentration. An oxide layer pattern is formed on the body region. A first trench is formed using the oxide layer pattern as an etching mask to perforate a predetermined portion of the body region having a first thickness. A body contact region of the second conductivity type having a high concentration is formed to surround the first trench by impurity ion implantation using the oxide layer pattern as an ion implantation mask. First spacer layers are formed to cover the sidewalls of the first trench and the sidewalls of the oxide layer pattern. A second trench is formed using the oxide layer pattern and the first spacer layers as etching masks to perforate a predetermined portion of the body region having a second thickness greater than the first thickness. A source region of the first conductivity type having a high concentration is formed to surround the second trench by impurity ion implantation using the oxide layer pattern and the first spacer layers as ion implantation masks. Second spacer layers are formed to cover the sidewalls of the second trench and the sidewalls of the first spacer layers. A third trench is formed to a predetermined depth of the epitaxial layer using the oxide layer pattern, the first spacer layers, and the second spacer layers as etching masks. A gate insulating layer is formed in the third trench. A gate conductive pattern is formed in the gate insulating layer. An oxide layer is formed on the gate conductive layer pattern. The first and second spacer layers are removed. A first metal electrode layer is formed to be electrically connected to the source region and the body contact region. A second metal electrode layer is formed to be electrically connected to the gate conductive layer pattern. A third metal electrode layer is formed to be electrically connected to the semiconductor substrate.

公开(公告)号：USD460186S1

公开(公告)日：2002-07-09

申请号：US29151907

申请日：2001-12-14

Applicant: Il-Yong Park

Designer： Il-Yong Park

公开(公告)号：US20100084708A1

公开(公告)日：2010-04-08

申请号：US12571468

申请日：2009-10-01

Applicant: Il-Yong Park

Inventor： Il-Yong Park

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/0873 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/66689 ,  H01L29/7817

Abstract: A semiconductor device includes a first conductivity-type deep well formed in a substrate, a plurality of device isolation layers formed in the substrate in which the first conductivity-type deep well is formed, a second conductivity-type well formed on a portion of the first conductivity-type deep well between two of the device isolation layers, a first gate pattern formed over a portion of the second conductivity-type well, a second gate pattern formed over one of the device isolation layers, a source region formed in an upper surface of the second conductivity-type well to adjoin a first side of the first gate pattern, a first drain region formed to include the interface between an upper surface of the second conductivity-type well adjoining a second side of the first gate pattern and an upper surface of the first conductivity-type deep well adjoining the second side of the first gate pattern, and a second drain region formed in an upper surface of the first conductivity-type deep well to be spaced from the second conductivity-type well.

Abstract translation: 半导体器件包括在衬底中形成的第一导电型深阱，形成在其中形成有第一导电型深阱的衬底中的多个器件隔离层，形成在第一导电型阱的一部分上的第二导电型阱 两个器件隔离层之间的第一导电型深阱，形成在第二导电类型阱的一部分上的第一栅极图案，形成在器件隔离层之一上的第二栅极图案，形成在上部 所述第二导电类型阱的表面邻接所述第一栅极图案的第一侧;第一漏极区，形成为包括所述第二导电类型阱的与所述第一栅极图案的第二侧相邻的上表面和 与第一栅极图案的第二侧邻接的第一导电型深阱的上表面和形成在第一导电类型深w的上表面中的第二漏极区 以与第二导电型阱间隔开。

公开(公告)号：US20090166736A1

公开(公告)日：2009-07-02

申请号：US12344544

申请日：2008-12-28

Applicant: Il-Yong Park

Inventor： Il-Yong Park

IPC: H01L29/808 ,  H01L21/336 ,  B05C11/00

CPC classification number: H01L29/7835 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376

Abstract: A lateral double diffused metal oxide semiconductor a lateral double diffused metal oxide semiconductor (LDMOS) transistor which may include a first conductive type semiconductor substrate and a shallow trench isolation film defining an active region in the substrate. A second conductive type body region may be disposed over a portion of the top of the semiconductor substrate. A first conductive type source region may be disposed in the top of the body region. A first conductive type extended drain region may be disposed over a portion of the top of the semiconductor substrate and spaced from the body region. A gate dielectric film covers surfaces of the second conductive type body region and first conductive type source region and a portion of the top of the first conductive type semiconductor substrate. A gate conductive film may extend from the first conductive type source region, over the gate dielectric film, over the shallow trench isolation film, and inside the shallow trench isolation film. Therefore, embodiments prevent the disturbance in flow of current in an on-state by the STI, making it possible to obtain improved on-state resistance characteristics.

Abstract translation: 横向双扩散金属氧化物半导体，横向双扩散金属氧化物半导体（LDMOS）晶体管，其可以包括在衬底中限定有源区的第一导电类型半导体衬底和浅沟槽隔离膜。 第二导电类型体区域可以设置在半导体衬底的顶部的一部分上方。 第一导电型源极区域可以设置在身体区域的顶部。 第一导电类型延伸漏极区域可以设置在半导体衬底的顶部的一部分上并与身体区域间隔开。 栅介电膜覆盖第二导电类型体区域和第一导电类型源极区域的表面和第一导电类型半导体衬底的顶部的一部分。 栅极导电膜可以从浅沟槽隔离膜上的第一导电型源极区域，栅极电介质膜上方，以及浅沟槽隔离膜内部延伸。 因此，实施例通过STI防止导通状态下的电流流动的干扰，从而可以获得改善的导通状态电阻特性。