公开(公告)号：US20130332703A1

公开(公告)日：2013-12-12

申请号：US13491781

申请日：2012-06-08

申请人： Ilie GARBACEA

发明人： Ilie GARBACEA

IPC分类号： G06F9/30

CPC分类号： G06F9/3851 ,  G06F9/384

摘要： A method of sharing a plurality of registers in a shared register pool among a plurality of microprocessor threads begins with a determination that a first instruction to be executed by a microprocessor in a first microprocessor thread requires a first logical register. Next a determination is made that a second instruction to be executed by the microprocessor in a second microprocessor thread requires a second logical register. A first physical register in the shared register pool is allocated to the first microprocessor thread for execution of the first instruction and the first logical register is mapped to the first physical register. A second physical register in the shared register pool is allocated to the second microprocessor thread for execution of the second instruction. Finally, the second logical register is mapped to the second physical register.

摘要翻译： 在多个微处理器线程之间共享共享寄存器池中的多个寄存器的方法开始于第一微处理器线程中由微处理器执行的第一指令需要第一逻辑寄存器。 接下来，确定由第二微处理器线程中的微处理器执行的第二指令需要第二逻辑寄存器。 共享寄存器池中的第一物理寄存器被分配给第一微处理器线程以执行第一指令，并且第一逻辑寄存器被映射到第一物理寄存器。 共享寄存器池中的第二物理寄存器被分配给第二微处理器线程以执行第二指令。 最后，第二个逻辑寄存器被映射到第二个物理寄存器。

公开(公告)号：US20130159667A1

公开(公告)日：2013-06-20

申请号：US13328792

申请日：2011-12-16

申请人： Ilie Garbacea

发明人： Ilie Garbacea

IPC分类号： G06F9/30 ,  G06F9/312 ,  G06F15/76

CPC分类号： G06F15/8053 ,  G06F9/30036

摘要： A computer has a memory adapted to store a first plurality of instructions encoded with a first vector size and a second plurality of instructions encoded with a second vector size. An execution unit executes the first plurality of instructions and the second plurality of instructions by processing vector units in a uniform manner regardless of vector size.

摘要翻译： 计算机具有适于存储用第一矢量大小编码的第一多个指令的存储器和用第二矢量大小编码的第二多个指令。 执行单元通过以均匀的方式处理向量单位来执行第一多个指令和第二多个指令，而不管矢量大小如何。

公开(公告)号：US08831093B2

公开(公告)日：2014-09-09

申请号：US13437183

申请日：2012-04-02

申请人： Ilie Garbacea ,  Lulin Chen ,  Jose R. Alvarez

发明人： Ilie Garbacea ,  Lulin Chen ,  Jose R. Alvarez

IPC分类号： H04B1/66 ,  H04N19/176 ,  H04N19/14 ,  H04N19/126 ,  H04N11/04

CPC分类号： H04N19/00096 ,  H04N19/126 ,  H04N19/14 ,  H04N19/176

摘要： In some embodiments, macroblock-level encoding parameters are assigned to weighted linear combinations of corresponding content-category-level encoding parameters. For example, a macroblock quantization parameter (QP) modulation is set to a weighted linear combination of content category QP modulations. Content categories may identify potentially overlapping content types such as sky, water, grass, skin, and red content. The combination weights may be similarity measures describing macroblock similarities to content categories. A macroblock may be associated with multiple content categories, with different similarity levels for different content categories. A similarity measure for a given macroblock with respect to a content category may be defined as a number (between 0 and 8) of neighboring macroblocks that meet a similarity condition, provided the macroblock meets a qualification condition. The similarity condition may be computationally simpler than the qualification condition. Content-category-level statistics are generated by combining block-level statistics. Content-category-level statistics may be used in encoding subsequent frames.

摘要翻译： 在一些实施例中，将宏块级编码参数分配给对应的内容类别级编码参数的加权线性组合。 例如，将宏块量化参数（QP）调制设置为内容类型QP调制的加权线性组合。 内容类别可能会识别潜在重叠的内容类型，如天空，水，草，皮肤和红色内容。 组合权重可以是描述与内容类别的宏块相似性的相似性度量。 宏块可以与多个内容类别相关联，具有针对不同内容类别的不同相似度级别。 如果宏块符合资格条件，则相对于内容类别的给定宏块的相似性度量可以被定义为满足相似性条件的相邻宏块之间的数目（在0和8之间）。 相似性条件可能比资格条件计算简单。 通过组合块级统计信息生成内容类别级统计信息。 内容类别级统计可用于对后续帧进行编码。

公开(公告)号：US08145880B1

公开(公告)日：2012-03-27

申请号：US12168853

申请日：2008-07-07

申请人： Sorin C Cismas ,  Ilie Garbacea

发明人： Sorin C Cismas ,  Ilie Garbacea

IPC分类号： G06F15/76

CPC分类号： G06F15/17381

摘要： According to some embodiments, an integrated circuit comprises a microprocessor matrix of mesh-interconnected matrix processors. Each processor comprises a data switch including a data switch link register and matrix routing logic. The data switch link register includes one or more matrix link-enable register fields specifying a link enable status (e.g. a message-independent, p-to-p, and/or broadcast link enable status) for each inter-processor matrix link of the processor. The matrix routing logic routes inter-processor messages according to the matrix link-enable register field(s). A particular link may be selected by a current matrix processor by selecting an ordered list of matrix links according to a relationship between ΔH and ΔV, and choosing the first enabled link in the selected list for routing. ΔH is the horizontal matrix position difference between the current (sender) processor and a destination processor, and ΔV is the vertical matrix position difference between the current and destination processors.

摘要翻译： 根据一些实施例，集成电路包括网状互连矩阵处理器的微处理器矩阵。 每个处理器包括包括数据交换链路寄存器和矩阵路由逻辑的数据交换机。 数据交换链路寄存器包括一个或多个矩阵链路使能寄存器字段，其指定针对每个处理器间矩阵链路的链路使能状态（例如，消息无关，p到p和/或广播链路使能状态） 处理器。 矩阵路由逻辑根据矩阵链路使能寄存器字段来路由处理器间消息。 可以由当前矩阵处理器通过根据＆Dgr; H和＆Dg​​r; V之间的关系选择矩阵链接的有序列表，并选择所选列表中的第一启用链路进行路由，来选择特定链路。 ＆Dgr; H是当前（发送者）处理器和目标处理器之间的水平矩阵位置差，＆Dgr; V是当前和目标处理器之间的垂直矩阵位置差。

公开(公告)号：US08131975B1

公开(公告)日：2012-03-06

申请号：US12168837

申请日：2008-07-07

申请人： Sorin C Cismas ,  Ilie Garbacea

发明人： Sorin C Cismas ,  Ilie Garbacea

IPC分类号： G06F15/76

CPC分类号： G06F15/8023 ,  G06F15/17381

摘要： In some embodiments, an integrated circuit comprises a microprocessor matrix including a plurality of mesh-interconnected matrix processors, wherein each matrix processor comprises a data switch configured to direct inter-processor communications within the matrix, and a mapping unit configured to generate a data switch functionality map for a plurality of data switches in the microprocessor matrix. The data switch functionality map is generated by sending a first message through the matrix, and, setting a first functionality status designation for the first data switch in the data switch functionality map upon receiving a reply to the first message from a first data switch through the matrix.

摘要翻译： 在一些实施例中，集成电路包括包括多个网状互连矩阵处理器的微处理器矩阵，其中每个矩阵处理器包括被配置为引导矩阵内的处理器间通信的数据交换机，以及配置成生成数据开关 用于微处理器矩阵中的多个数据交换机的功能图。 通过发送第一消息通过矩阵来生成数据交换功能映射，并且在从第一数据交换机接收到对第一消息的回复时，通过数据交换功能映射设置数据交换功能映射中的第一数据交换机的第一功能状态指定 矩阵。

公开(公告)号：US08149909B1

公开(公告)日：2012-04-03

申请号：US11249213

申请日：2005-10-13

申请人： Ilie Garbacea ,  Lulin Chen ,  Jose R. Alvarez

发明人： Ilie Garbacea ,  Lulin Chen ,  Jose R. Alvarez

IPC分类号： H04N7/12 ,  H04N11/04

CPC分类号： H04N19/00096 ,  H04N19/126 ,  H04N19/14 ,  H04N19/176

摘要： In some embodiments, macroblock-level encoding parameters are assigned to weighted Linear combinations of corresponding content-category-level encoding parameters. A macroblock quantization parameter (QP) modulation is set to a weighted linear combination of content category QP modulations. Content categories may identify potentially overlapping content types. The combination weights may be similarity measures describing macroblock similarities to content categories. A macroblock may be associated with multiple content categories, with different similarity levels for different content categories. A similarity measure for a given macroblock with respect to a content category may be defined as a number (between 0 and 8) of neighboring macroblocks that meet a similarity condition, provided the macroblock meets a qualification condition. The similarity condition may be computationally simpler than the qualification condition. Content-category-level statistics are generated by combining block-level statistics. Content-category-level statistics may be used in encoding subsequent frames.

摘要翻译： 在一些实施例中，宏块级编码参数被分配给相应内容类别级编码参数的加权线性组合。 宏块量化参数（QP）调制被设置为内容类别QP调制的加权线性组合。 内容类别可能会识别可能重叠的内容类型。 组合权重可以是描述与内容类别的宏块相似性的相似性度量。 宏块可以与多个内容类别相关联，具有针对不同内容类别的不同相似度级别。 如果宏块符合资格条件，则相对于内容类别的给定宏块的相似性度量可以被定义为满足相似性条件的相邻宏块之间的数目（在0和8之间）。 相似性条件可能比资格条件计算简单。 通过组合块级统计信息生成内容类别级统计信息。 内容类别级统计可用于对后续帧进行编码。

公开(公告)号：US08126283B1

公开(公告)日：2012-02-28

申请号：US11250102

申请日：2005-10-13

申请人： Ilie Garbacea ,  Lulin Chen ,  Jose R. Alvarez

发明人： Ilie Garbacea ,  Lulin Chen ,  Jose R. Alvarez

IPC分类号： G06K9/46

CPC分类号： G06F17/30831 ,  G06F17/3079 ,  H04N19/124 ,  H04N19/136 ,  H04N19/142 ,  H04N19/147 ,  H04N19/149 ,  H04N19/176 ,  H04N19/196 ,  H04N19/85

摘要： In some embodiments, content-category-level encoding statistical indicators (statistics) are assigned to weighted linear combinations of corresponding macroblock-level statistics. Content categories may identify potentially overlapping content types such as sky, water, grass, skin, and red content. The combination weights may be similarity measures describing macroblock similarities to content categories. A given macroblock may be associated with multiple content categories, with different similarity levels for different content categories. A similarity measure for a given macroblock with respect to a content category may be defined as a number (between 0 and 8) of neighboring macroblocks that meet a similarity condition, provided the macroblock meets a qualification condition. The similarity condition may be computationally simpler than the qualification condition. Macroblock-level encoding parameters are generated by combining content-category-level parameters.

摘要翻译： 在一些实施例中，内容类别级编码统计指标（统计）被分配给相应宏块级统计的加权线性组合。 内容类别可能会识别潜在重叠的内容类型，如天空，水，草，皮肤和红色内容。 组合权重可以是描述与内容类别的宏块相似性的相似性度量。 给定宏块可以与多个内容类别相关联，具有针对不同内容类别的不同相似度级别。 如果宏块符合资格条件，则相对于内容类别的给定宏块的相似性度量可以被定义为满足相似性条件的相邻宏块之间的数目（在0和8之间）。 相似性条件可能比资格条件计算简单。 通过组合内容类别级参数来生成宏块级编码参数。

公开(公告)号：US07958341B1

公开(公告)日：2011-06-07

申请号：US12168861

申请日：2008-07-07

申请人： Sorin C Cismas ,  Ilie Garbacea

发明人： Sorin C Cismas ,  Ilie Garbacea

IPC分类号： G06F13/14

CPC分类号： G06F15/17381 ,  G06F15/167

摘要： In some embodiments, each matrix processor in a matrix of mesh-interconnected matrix processors includes an instruction processing pipeline, and a hardware data switch capable of streaming data to/from one or more inter-processor matrix links and/or a matrix processor local memory links in response to execution of a data streaming instruction by the instruction processing pipeline. The data switch can transfer each data stream, which includes multiple words, at wire speed, one word per cycle. After initiating a data stream, the processing pipeline can execute other instructions, including streaming instructions, while a stream transfer is in progress. Different data streaming instructions may be used to transfer data streams from local memory to one or more inter-processor links, from an inter-processor link to local memory, from an inter-processor link to one or more inter-processor links, and from an inter-processor link to one or more inter-processor links and synchronously to local memory.

摘要翻译： 在一些实施例中，网状互连矩阵处理器的矩阵中的每个矩阵处理器包括指令处理流水线和能够将数据传送到一个或多个处理器间矩阵链路和/或矩阵处理器本地存储器的硬件​​数据交换机 响应于指令处理流水线执行数据流指令的链接。 数据交换机可以以线速度传输每个包含多个字的数据流，每个周期一个字。 在启动数据流之后，处理流水线可以执行其他指令，包括流指令，而流传输正在进行中。 可以使用不同的数据流指令将数据流从本地存储器传送到从处理器间链路到本地存储器的一个或多个处理器间链路，从处理器间链路到一个或多个处理器间链路， 与一个或多个处理器间链路并且与本地存储器同步的处理器间链路。

公开(公告)号：US10534614B2

公开(公告)日：2020-01-14

申请号：US13491781

申请日：2012-06-08

申请人： Ilie Garbacea

发明人： Ilie Garbacea

IPC分类号： G06F9/38

摘要： A method of sharing a plurality of registers in a shared register pool among a plurality of microprocessor threads begins with a determination that a first instruction to be executed by a microprocessor in a first microprocessor thread requires a first logical register. Next a determination is made that a second instruction to be executed by the microprocessor in a second microprocessor thread requires a second logical register. A first physical register in the shared register pool is allocated to the first microprocessor thread for execution of the first instruction and the first logical register is mapped to the first physical register. A second physical register in the shared register pool is allocated to the second microprocessor thread for execution of the second instruction. Finally, the second logical register is mapped to the second physical register.

公开(公告)号：US08094716B1

公开(公告)日：2012-01-10

申请号：US11268803

申请日：2005-11-08

申请人： Lulin Chen ,  Ilie Garbacea

发明人： Lulin Chen ,  Ilie Garbacea

IPC分类号： H04N7/12

CPC分类号： H04N19/19 ,  H04N19/14 ,  H04N19/147 ,  H04N19/18 ,  H04N19/61

摘要： A method for hybrid video coding is disclosed. The method generally includes the steps of (A) calculating a bit rate based on a percentage of quantized zero coefficients resulting from encoding a plurality of components of a video signal, (B) calculating a distortion based on the percentage of quantized zero coefficients, (C) calculating a plurality of variances of a plurality of prediction error pictures and (D) calculating an adaptive Lagrangian multiplier in a Lagrangian rate-distortion optimization as a function of the bit rate, the distortion and the variance to minimize a Lagrangian cost.

摘要翻译： 公开了一种混合视频编码方法。 该方法通常包括以下步骤：（A）基于由视频信号的多个分量的编码产生的量化零系数的百分比来计算比特率，（B）基于量化零系数的百分比来计算失真（ C）计算多个预测误差图像的多个方差，以及（D）根据比特率，所述失真和方差来计算拉格朗日速率失真优化中的自适应拉格朗日乘数以使拉格朗日成本最小化。