公开(公告)号：US08060851B2

公开(公告)日：2011-11-15

申请号：US11850342

申请日：2007-09-05

申请人： Richard C. Dokken ,  Gerald S. Chan ,  Jacob J Orbon ,  Alfred L Crouch

发明人： Richard C. Dokken ,  Gerald S. Chan ,  Jacob J Orbon ,  Alfred L Crouch

IPC分类号： G06F17/50

CPC分类号： G01R31/318541 ,  G01R31/318552

摘要： A method for operating a secure semiconductor IP access server to support failure analysis. A client presents a test failure and failure type to an automated server which traverses an electronic product design, definition, and test database to report specifically those components and interconnect likely to cause the failure with geometrical information which may be displayed on the client. Other aspects of semiconductor IP are protected by the server by limiting the trace mechanism and renaming components.

摘要翻译： 一种用于操作安全半导体IP访问服务器以支持故障分析的方法。 客户端向自动化服务器呈现测试失败和故障类型，该服务器遍历电子产品设计，定义和测试数据库，以具体报告那些组件和互连可能导致故障与可能在客户端上显示的几何信息。 半导体IP的其他方面由服务器通过限制跟踪机制和重命名组件来保护。

公开(公告)号：US07760929B2

公开(公告)日：2010-07-20

申请号：US11553745

申请日：2006-10-27

申请人： Jacob J. Orbon ,  Youval Nehmadi ,  Ofer Bokobza ,  Ariel Ben-Porath ,  Erez Ravid ,  Rinat Shimshi ,  Vicky Svidenko

发明人： Jacob J. Orbon ,  Youval Nehmadi ,  Ofer Bokobza ,  Ariel Ben-Porath ,  Erez Ravid ,  Rinat Shimshi ,  Vicky Svidenko

IPC分类号： G06K9/00

CPC分类号： G03F7/7065 ,  G03F1/84

摘要： Methods and apparatus for categorizing defects on workpieces, such as semiconductor wafers and masks used in lithographically writing patterns into such wafers are provided. For some embodiments, by analyzing the layout in the neighborhood of the defect, and matching it to similar defected neighborhoods in different locations across the die, defects may be categorized by common structures in which they occur.

摘要翻译： 提供了用于将工件上的缺陷（例如半导体晶片和用于将这种晶片刻画图案所用的掩模）分类的方法和装置。 对于一些实施例，通过分析缺陷附近的布局，并且将其匹配到跨越裸片的不同位置中的类似的缺陷邻域，可以通过它们出现的共同结构对缺陷进行分类。

公开(公告)号：US07760347B2

公开(公告)日：2010-07-20

申请号：US11383395

申请日：2006-05-15

申请人： Youval Nehmadi ,  Ofer Bokobza ,  Ariel Ben-Porath ,  Erez Ravid ,  Rinat Shishi ,  Vicky Svidenko ,  Gilad Almogy ,  Jacob J. Orbon, Jr.

发明人： Youval Nehmadi ,  Ofer Bokobza ,  Ariel Ben-Porath ,  Erez Ravid ,  Rinat Shishi ,  Vicky Svidenko ,  Gilad Almogy ,  Jacob J. Orbon, Jr.

IPC分类号： G01N21/00

CPC分类号： G03F7/7065 ,  G03F1/84

摘要： Methods and apparatus for categorizing defects on workpieces, such as semiconductor wafers and masks used in lithographically writing patterns into such wafers are provided. For some embodiments, by analyzing the layout in the neighborhood of the defect, and matching it to similar defected neighborhoods in different locations across the die, defects may be categorized by common structures in which they occur.

摘要翻译： 提供了用于将工件上的缺陷（例如半导体晶片和用于将这种晶片刻画图案所用的掩模）分类的方法和装置。 对于一些实施例，通过分析缺陷附近的布局，并且将其匹配到跨越裸片的不同位置中的类似的缺陷邻域，可以通过它们出现的共同结构对缺陷进行分类。

公开(公告)号：US20100031092A1

公开(公告)日：2010-02-04

申请号：US11850342

申请日：2007-09-05

申请人： RICHARD C. DOKKEN ,  GERALD S. CHAN ,  JACOB J. ORBON ,  ALFRED L. CROUCH

发明人： RICHARD C. DOKKEN ,  GERALD S. CHAN ,  JACOB J. ORBON ,  ALFRED L. CROUCH

IPC分类号： G06F11/34

CPC分类号： G01R31/318541 ,  G01R31/318552

摘要： A method for operating a secure semiconductor IP access server to support failure analysis. A client presents a test failure and failure type to an automated server which traverses an electronic product design, definition, and test database to report specifically those components and interconnect likely to cause the failure with geometrical information which may be displayed on the client. Other aspects of semiconductor IP are protected by the server by limiting the trace mechanism and renaming components.

摘要翻译： 一种用于操作安全半导体IP访问服务器以支持故障分析的方法。 客户端向自动化服务器呈现测试失败和故障类型，该服务器遍历电子产品设计，定义和测试数据库，以具体报告那些组件和互连可能导致故障与可能在客户端上显示的几何信息。 半导体IP的其他方面由服务器通过限制跟踪机制和重命名组件来保护。

公开(公告)号：US20170220706A1

公开(公告)日：2017-08-03

申请号：US13822625

申请日：2010-09-13

申请人： Jacob J. ORBON ,  Eric VOLKERINK

发明人： Jacob J. ORBON ,  Eric VOLKERINK

IPC分类号： G06F17/50

CPC分类号： G06F17/504 ,  G06F2217/10

摘要： A method for statistically analyzing structural test information to identify at least one yield loss mechanism includes executing a plurality of instructions on a computer system. The executed instructions cause the computer system to perform the steps of: 1) identifying potential root causes for items of structural test information obtained for a plurality of semiconductor devices; 2) statistically analyzing the items of structural test information to identify at least one non-random device failure signature within the items of structural test information; and 3) identifying from the potential root causes a probable root cause for at least a first of the at least one non-random device failure signature.