公开(公告)号：US08000120B2

公开(公告)日：2011-08-16

申请号：US12436883

申请日：2009-05-07

申请人： Jinn-Shyan Wang ,  Tai-An Chen

发明人： Jinn-Shyan Wang ,  Tai-An Chen

IPC分类号： G11C15/00

CPC分类号： G11C15/04 ,  G11C7/02

摘要： A read, write, and match circuit for a low-voltage content addressable memory. A write circuit inputs signals for storing data in the memory cells, a read circuit retrieves the stored data from the memory cells, and a match circuit compares the data stored in the memory cell with the data searched by the match circuit. The circuits for writing, reading and matching are separated from each other and exempt from mutual interference.

摘要翻译： 用于低电压内容可寻址存储器的读，写和匹配电路。 写入电路输入用于将数据存储在存储器单元中的信号，读取电路从存储器单元检索存储的数据，并且匹配电路将存储单元中存储的数据与由匹配电路搜索的数据进行比较。 用于写入，读取和匹配的电路彼此分离，免除相互干扰。

公开(公告)号：US07756236B2

公开(公告)日：2010-07-13

申请号：US11757833

申请日：2007-06-04

申请人： Jinn-Shyan Wang ,  Yi-Ming Wang

发明人： Jinn-Shyan Wang ,  Yi-Ming Wang

IPC分类号： H03D3/24 ,  H03D13/00

CPC分类号： H03D13/004

摘要： A phase detector is described, comprising a pair of output-latched half-transparent (OLHT) module each receiving two input terminals with an inverse connection relationship with respect to two input signals as compared to each other, wherein each OLHT module of the pair comprises two stages of logic operation unit connected in series and a latch circuit electrically connected to a latter one of the two stages of logic operation unit and latching and output an output signal.

摘要翻译： 描述了一种相位检测器，其包括一对输出锁存的半透明（OLHT）模块，每个模块相对于彼此相对于两个输入信号接收两个具有反连接关系的输入端子，其中该对中的每个OLHT模块包括 串联连接的两级逻辑运算单元和与两级逻辑运算单元中的后级逻辑运算单元电连接的锁存电路，并锁存并输出输出信号。

公开(公告)号：US20100142242A1

公开(公告)日：2010-06-10

申请号：US12436883

申请日：2009-05-07

申请人： Jinn-Shyan Wang ,  Tai-An Chen

发明人： Jinn-Shyan Wang ,  Tai-An Chen

IPC分类号： G11C15/00 ,  G11C7/00

CPC分类号： G11C15/04 ,  G11C7/02

摘要： The present invention discloses a read and match circuit for a low-voltage content addressable memory, wherein the write circuit inputs the signals needing storing into the memory cells, and the read circuit retrieves the stored signals from the memory cells, and the match circuit compares the data stored in the memory cell with the data searched by the match circuit. As the circuits for writing, reading and matching are separated from each other and exempt from mutual interference, the present invention can achieve high reliability and low power consumption under a low-voltage operation environment without using a special fabrication process. In the present invention, the circuit is optimized to meet different requirements. The present invention enables the user to determine whether to have high speed or to have low power consumption. Further, the present invention can overcome the problems of current leakage and noise allowance in a low-voltage environment.

摘要翻译： 本发明公开了一种用于低电压内容可寻址存储器的读取和匹配电路，其中写入电路将需要存储的信号输入到存储器单元中，并且读取电路从存储器单元检索存储的信号，并且匹配电路比较 存储在存储单元中的数据与匹配电路搜索的数据。 由于写入，读取和匹配的电路彼此分离并且免除相互干扰，因此本发明可以在低电压操作环境下实现高可靠性和低功耗，而不使用特殊的制造工艺。 在本发明中，电路被优化以满足不同的要求。 本发明使得用户能够确定是高速还是低功耗。 此外，本发明可以克服在低电压环境下的电流泄漏和噪声容限的问题。

公开(公告)号：US07667993B2

公开(公告)日：2010-02-23

申请号：US11907524

申请日：2007-10-12

申请人： Chao-Ching Wang ,  Chieh-Jen Cheng ,  Jinn-Shyan Wang ,  Tien-Fu Chen

发明人： Chao-Ching Wang ,  Chieh-Jen Cheng ,  Jinn-Shyan Wang ,  Tien-Fu Chen

IPC分类号： G11C15/00

CPC分类号： G11C15/04 ,  G11C7/1075

摘要： A dual-ported AND-type match-line circuit includes at least one dual-ported dynamic AND gate. The dual-ported dynamic AND gate includes a group of CAM cells and a dual-ported dynamic circuit. A group of CAM cells connected to a dual-ported dynamic circuit and to the GND. The dual-ported dynamic circuit is connected to a group of CAM cells. The dual-ported dynamic circuit includes a setting circuit, a first directing circuit, a second directing circuit, a first AND dynamic output circuit and a second AND dynamic output circuit.

摘要翻译： 双端口AND型匹配线电路包括至少一个双端口动态AND门。 双端口动态和门包括一组CAM单元和双端口动态电路。 一组CAM单元连接到双端口动态电路和GND。 双端口动态电路连接到一组CAM单元。 双端口动态电路包括设置电路，第一引导电路，第二引导电路，第一AND动态输出电路和第二AND动态输出电路。

公开(公告)号：US07649405B2

公开(公告)日：2010-01-19

申请号：US11415210

申请日：2006-05-02

申请人： Jinn-Shyan Wang ,  Hung-Yu Li

发明人： Jinn-Shyan Wang ,  Hung-Yu Li

IPC分类号： G05F1/10 ,  G05F3/02

CPC分类号： H03K19/0016

摘要： A leakage current control circuit with a single low voltage power supply is provided. The circuit includes a first power supply line, a second power supply line, a ground line, a high voltage generating circuit, a power transistor and a control circuit. The high voltage generating circuit generates a voltage in response to an internal sleep signal. The gate electrode of the power transistor is connected to the output of the high-voltage generating circuit such that the power transistor is controlled by the high voltage generating circuit. When the power transistor turns on, the circuit is in operation mode; when the power transistor is off, the circuit is in sleep mode. The control circuit connects to the first power line, the second power line, and the ground line to output the internal sleep signal in response to the sleep signal.

摘要翻译： 提供具有单个低电压电源的漏电流控制电路。 该电路包括第一电源线，第二电源线，地线，高电压发生电路，功率晶体管和控制电路。 高电压产生电路响应于内部睡眠信号产生电压。 功率晶体管的栅电极连接到高电压发生电路的输出，使得功率晶体管由高电压产生电路控制。 当功率晶体管导通时，电路处于工作模式; 当功率晶体管关闭时，电路处于睡眠模式。 控制电路连接到第一电力线，第二电力线和地线，以响应于睡眠信号输出内部睡眠信号。

公开(公告)号：US20080225939A1

公开(公告)日：2008-09-18

申请号：US11686571

申请日：2007-03-15

申请人： JIUN-IN GUO ,  KUAN-HUNG CHEN ,  JINN-SHYAN WANG ,  YU-MIN CHEN ,  YUAN-SUN CHU

发明人： JIUN-IN GUO ,  KUAN-HUNG CHEN ,  JINN-SHYAN WANG ,  YU-MIN CHEN ,  YUAN-SUN CHU

IPC分类号： H04B1/66

CPC分类号： H04N19/43 ,  H04N19/42

摘要： The present invention discloses a multifunctional video encoding circuit system capable of performing six types of operations: addition, subtraction, multiplication, multiply-accumulation, interpolation, and absolute difference summation. A partial product generation part, a partial product reduction part and an accumulation part of the circuit system are equipped with a virtual power suppression unit each for reducing the power consumption of the partial product generation part, the partial product reduction part and the accumulation part, so as to reduce the power consumption of the multifunctional video encoding circuit system.

摘要翻译： 本发明公开了一种能够进行加法，减法，乘法，乘法累积，插补和绝对差分求和的六种操作的多功能视频编码电路系统。 部分产品生成部分，部分产品减少部分和电路系统的累积部分配备有虚拟功率抑制单元，每个虚拟功率抑制单元用于降低部分产品生成部分，部分产品减少部分和累积部分的功耗， 从而降低多功能视频编码电路系统的功耗。

公开(公告)号：US20080063047A1

公开(公告)日：2008-03-13

申请号：US11517348

申请日：2006-09-08

申请人： Jiun-In Guo ,  Jinn-Shyan Wang ,  Jia-Wei Chen

发明人： Jiun-In Guo ,  Jinn-Shyan Wang ,  Jia-Wei Chen

IPC分类号： H04B1/66

CPC分类号： H04N19/42 ,  H04N19/11 ,  H04N19/176 ,  H04N19/61

摘要： An intra prediction circuit device applied to the H.264 video coding standard is provided. The intra prediction device uses a method of decreasing the repeated operations of the shared terms of the video pixel data to reduce the circuit computation and simplify the hardware architecture. In the intra prediction scheme, the computational complexity can be lessened by implementing not only the adder based method but also decomposition technique to simplify the algorithm of the intra prediction.

摘要翻译： 提供了应用于H.264视频编码标准的帧内预测电路装置。 帧内预测装置使用减少视频像素数据的共享项的重复操作以减少电路计算并简化硬件体系结构的方法。 在帧内预测方案中，通过不仅采用基于加法器的方法，而且通过实现分解技术来简化帧内预测算法，可以减少计算复杂度。

公开(公告)号：US20080056372A1

公开(公告)日：2008-03-06

申请号：US11513277

申请日：2006-08-31

申请人： Zhi-Xin Lin ,  Jinn-Shyan Wang ,  Ching-Wei Yeh

发明人： Zhi-Xin Lin ,  Jinn-Shyan Wang ,  Ching-Wei Yeh

IPC分类号： H04B1/66 ,  G06K9/40 ,  H04N11/02 ,  H04N11/04 ,  H04N7/12

CPC分类号： H04N19/63 ,  G06K9/482

摘要： An apparatus for processing an image with a discrete wavelet transform is provided. For one-dimensional circuit, the method changes conventional image data processing flow and uses common product of sequential calculations with respect to the time axis. The calculations for input data are not repeated so that components of the hardware architecture are minimized. For two-dimensional circuit, the method uses an external data scanning method to eliminate an external memory, transposing buffer, from a transforming circuit.

摘要翻译： 提供一种用离散小波变换处理图像的装置。 对于一维电路，该方法改变了常规图像数据处理流程，并且使用了相对于时间轴的顺序计算的公共产物。 不重复输入数据的计算，从而使硬件架构的组件最小化。 对于二维电路，该方法使用外部数据扫描方法来消除来自变换电路的外部存储器，转置缓冲器。

公开(公告)号：US07224197B2

公开(公告)日：2007-05-29

申请号：US11211666

申请日：2005-08-26

申请人： Jinn-Shyan Wang ,  Hung-Yu Li

发明人： Jinn-Shyan Wang ,  Hung-Yu Li

IPC分类号： H03K3/289

CPC分类号： H03K3/35625

摘要： The present invention discloses a flip-flop implemented with metal-oxide semiconductors using a single low-voltage power supply and a control method thereof, wherein an external control signal is input to a power switch in order to turn on the power switch for an active mode or to turn off the power switch for a sleep mode and inputting an external sleep control signal; the power switch is used to control a combinational circuit to enter into the active or the sleep mode, and the combinational circuit is connected to a virtual power supply; an internal clock signal is separately input to a master stage and a slave stage of the flip-flop, and whether to enter into the sleep mode or the active mode is determined by the voltage level of the internal clock signal. In the present invention, all the logic gates of the combinational circuit are formed of low-threshold CMOS's, which enables the present invention to maintain a given operation speed at a lower voltage. The flip-flop of the present invention is formed of both low-threshold and high-threshold elements, whereby not only the operation speed can be maintained but also the leakage current can be suppressed spontaneously, and further, the wake-up time can be shortened.

公开(公告)号：US5225832A

公开(公告)日：1993-07-06

申请号：US836076

申请日：1992-02-13

申请人： Jinn-Shyan Wang ,  Yung-Jung Jan

发明人： Jinn-Shyan Wang ,  Yung-Jung Jan

IPC分类号： H04N5/92 ,  H03K19/177 ,  H03M7/40 ,  H03M7/42 ,  H03M7/46 ,  H04N7/26

CPC分类号： H03M7/425

摘要： A high speed variable length decoder can decode more than one code word in one cycle. A PLA used in the decoder includes extra product lines and extra output lines in order to detect and decode two successive short length code words in one cycle. When two short length code words are detected, a corresponding extra product line is activated and the two code words are decoded in the same cycle using an extra output line. For a digital video compression system, a significant speed-up in the variable length decoder can be achieved by the invention.

摘要翻译： 高速可变长度解码器可以在一个周期中解码多个码字。 在解码器中使用的PLA包括额外的产品线和额外的输出线，以便在一个周期内检测和解码两个连续的短长度码字。 当检测到两个短长度的码字时，激活相应的额外乘积线，并且使用额外的输出线在相同的周期中对两个码字进行解码。 对于数字视频压缩系统，通过本发明可以实现可变长度解码器中的显着加速。