公开(公告)号：US06928600B2

公开(公告)日：2005-08-09

申请号：US10122185

申请日：2002-04-16

申请人： Chi-Fang Li ,  Wern-Ho Sheen ,  Yuan-Sun Chu ,  Jan-Shin Ho ,  Yuan-Tzu Ting

发明人： Chi-Fang Li ,  Wern-Ho Sheen ,  Yuan-Sun Chu ,  Jan-Shin Ho ,  Yuan-Tzu Ting

IPC分类号： H03M13/15 ,  H03M13/33

CPC分类号： H03M13/15

摘要： A kind of folding systolic array architecture for a CFRS decoding circuit that applies to a cell search in a wideband code division multiple access system. The invention involves using a systolic array for its decoding circuit and using a kind of folding technology to reduce the area of the systolic array. The systolic array for the decoding circuit comprises an input pattern generator, a processing element array designed in the form of a systolic array and a boundary processing element array. Given the skewed-form output results required by the systolic array and generated by the input pattern generator, the processing element array makes a set of correlating comparisons, and outputs the results of the correlating comparisons to the boundary processing elements, so as to acquire the decoding results required by the CFRS decoding. The results indicate the frame boundary and scrambling code groups of the cell search in a wideband code division multiple access system.

摘要翻译： 一种用于CFRS解码电路的折叠式收缩阵列架构，适用于宽带码分多址系统中的小区搜索。 本发明涉及使用收缩阵列作为其解码电路，并使用一种折叠技术来减小收缩阵列的面积。 用于解码电路的收缩阵列包括输入图案生成器，以心轴阵列和边界处理元件阵列的形式设计的处理元件阵列。 给定收缩阵列所需的偏斜形式输出结果并由输入模式发生器产生，处理单元阵列进行一组相关比较，并将相关比较的结果输出到边界处理单元，以获得 CFRS解码所需的解码结果。 结果表明宽带码分多址系统中小区搜索的帧边界和扰码组。

公开(公告)号：US20080225939A1

公开(公告)日：2008-09-18

申请号：US11686571

申请日：2007-03-15

申请人： JIUN-IN GUO ,  KUAN-HUNG CHEN ,  JINN-SHYAN WANG ,  YU-MIN CHEN ,  YUAN-SUN CHU

发明人： JIUN-IN GUO ,  KUAN-HUNG CHEN ,  JINN-SHYAN WANG ,  YU-MIN CHEN ,  YUAN-SUN CHU

IPC分类号： H04B1/66

CPC分类号： H04N19/43 ,  H04N19/42

摘要： The present invention discloses a multifunctional video encoding circuit system capable of performing six types of operations: addition, subtraction, multiplication, multiply-accumulation, interpolation, and absolute difference summation. A partial product generation part, a partial product reduction part and an accumulation part of the circuit system are equipped with a virtual power suppression unit each for reducing the power consumption of the partial product generation part, the partial product reduction part and the accumulation part, so as to reduce the power consumption of the multifunctional video encoding circuit system.

摘要翻译： 本发明公开了一种能够进行加法，减法，乘法，乘法累积，插补和绝对差分求和的六种操作的多功能视频编码电路系统。 部分产品生成部分，部分产品减少部分和电路系统的累积部分配备有虚拟功率抑制单元，每个虚拟功率抑制单元用于降低部分产品生成部分，部分产品减少部分和累积部分的功耗， 从而降低多功能视频编码电路系统的功耗。

公开(公告)号：US08166377B2

公开(公告)日：2012-04-24

申请号：US12423897

申请日：2009-04-15

申请人： Yuan-Sun Chu ,  Yi-Ren Chen ,  Chia-Ying Huang ,  Chi-Fang Li

发明人： Yuan-Sun Chu ,  Yi-Ren Chen ,  Chia-Ying Huang ,  Chi-Fang Li

IPC分类号： H03M13/00

CPC分类号： H04L1/0052 ,  H03M13/15 ,  H04L1/0057

摘要： The present invention discloses a configurable hierarchical comma-free Reed-Solomon decoding circuit and a method thereof. The design is based on an original hierarchical parallel architecture which not only completes a decoding process faster than conventional decoder, but also utilizes less hardware to perform various algorithms with less power consumed. The architecture of the present invention has higher decoding rate than the conventional systolic architecture by a cycle ratio of 22 to 94. Further, the present invention does not require the use of ROM to store 64 sets of codewords and uses logic gates less than one fourth of the logic gates than conventional systolic architecture. As a result, the circuit of the present invention occupies less area than the conventional architecture. The circuit of the present invention is also configurable for different applications, so it can always find an optimal compromise between speed and power consumption for various decoding requirements.

摘要翻译： 本发明公开了一种可配置分层无间断里德 - 索罗门解码电路及其方法。 该设计基于原始的分层并行架构，其不仅比传统解码器更快地完成解码过程，而且还利用较少的硬件来执行具有较少功耗的各种算法。 本发明的架构具有比常规收缩结构更高的解码速率，循环比为22至94.此外，本发明不需要使用ROM来存储64组码字，并且使用小于四分之一的逻辑门 的逻辑门比传统的收缩结构。 结果，本发明的电路占用的面积小于常规架构。 本发明的电路也可以针对不同的应用进行配置，因此它可以总是在各种解码要求之间找到速度和功耗之间的最佳折中。

公开(公告)号：US08000352B2

公开(公告)日：2011-08-16

申请号：US12419911

申请日：2009-04-07

申请人： Yuan-Sun Chu ,  Ting-Huan Li ,  Yi-Ren Chen ,  Chia-Ying Huang ,  Kuo-Hua Pu ,  Chi-Fang Li

发明人： Yuan-Sun Chu ,  Ting-Huan Li ,  Yi-Ren Chen ,  Chia-Ying Huang ,  Kuo-Hua Pu ,  Chi-Fang Li

IPC分类号： H04J3/06

CPC分类号： H04W56/00 ,  H04B1/7075 ,  H04B2201/70707 ,  H04W92/10

摘要： A synchronizer for a communication device and an access point, which is installed inside the communication device and comprises a coefficient generator generating a set of coefficient code. A parallel-to-serial converter receives a set of input code from an access point, performs a parallel-to-serial conversion on the set of input code and outputs a result. A coefficient element array includes a plurality of coefficient elements interconnecting with each other. Each of the coefficient elements receives the set of input code from the parallel-to-serial converter and receives the set of coefficient code, and then performs a passive or active correlation operation on the set of input code and the set of coefficient code to output a correlation value to the access point for synchronizing signals of the communication device and the access point.

摘要翻译： 一种用于通信设备和接入点的同步器，其安装在通信设备内部并且包括产生一组系数代码的系数发生器。 并行到串行转换器从接入点接收一组输入代码，对该组输入代码执行并行到串行转换并输出结果。 系数元素阵列包括彼此互连的多个系数元素。 每个系数元件从并行到串行转换器接收一组输入代码并接收该系数码集合，然后对该组输入码和该系数码组进行无源或主动相关运算以输出 与用于同步通信设备和接入点的信号的接入点的相关值。

公开(公告)号：US20100142506A1

公开(公告)日：2010-06-10

申请号：US12419911

申请日：2009-04-07

申请人： Yuan-Sun Chu ,  Ting-Huan Li ,  Yi-Ren Chen ,  Chia-Ying Huang ,  Kuo-Hua Pu ,  Chi-Fang Li

发明人： Yuan-Sun Chu ,  Ting-Huan Li ,  Yi-Ren Chen ,  Chia-Ying Huang ,  Kuo-Hua Pu ,  Chi-Fang Li

IPC分类号： H04J3/06 ,  H04B7/216

CPC分类号： H04W56/00 ,  H04B1/7075 ,  H04B2201/70707 ,  H04W92/10

摘要： The present invention discloses a synchronizer for a communication device and an access point, which is installed inside the communication device and comprises a coefficient generator generating a set of coefficient code; a parallel-to-serial converter receiving a set of input code from an access point, performing a parallel-to-serial conversion on the set of input code and outputting a result; and a coefficient element array including a plurality of coefficient elements interconnecting with each other, wherein each of the coefficient elements receives the set of input code from the parallel-to-serial converter and receives the set of coefficient code, and then performs a passive or active correlation operation on the set of input code and the set of coefficient code to output a correlation value to the access point for synchronizing signals of the communication device and the access point. The present invention has the synchronization functions of two communication systems—WCDMA and CDMA 2000, and thus can reduce the fabrication cost and increase convenience of communication.

摘要翻译： 本发明公开了一种用于通信设备和接入点的同步器，其安装在通信设备内部并且包括产生一组系数代码的系数发生器; 并行 - 串行转换器，从接入点接收一组输入代码，对所述一组输入代码执行并行到串行转换并输出结果; 以及包括彼此互连的多个系数元素的系数元素阵列，其中每个系数元件从并行到串行转换器接收一组输入代码并接收该组系数代码，然后执行被动或 对输入代码集合和系数码集合进行主动相关运算，以将相关值输出到用于同步通信设备和接入点的信号的接入点。 本发明具有WCDMA和CDMA2000两种通信系统的同步功能，从而可以降低制造成本并增加通信的便利性。

公开(公告)号：US07051263B2

公开(公告)日：2006-05-23

申请号：US10120536

申请日：2002-04-12

申请人： Chi-Fang Li ,  Wern-Ho Sheen ,  Yuan-Sun Chu ,  Jan-Shin Ho ,  Yuan-Tzu Ting

发明人： Chi-Fang Li ,  Wern-Ho Sheen ,  Yuan-Sun Chu ,  Jan-Shin Ho ,  Yuan-Tzu Ting

IPC分类号： H03M13/15

CPC分类号： H03M13/15

摘要： A Comma-Free Reed-Solomon decoding circuit based on systolic array architecture that applies to a cell search in a wideband code division multiple access system, and more particularly a decoding circuit that employs a systolic array in its circuit structure. The systolic array for the decoding circuit comprises an input pattern generator, a processing element array designed in the form of a systolic array and a boundary processing element array. Given the skewed-form output results required by the systolic array and generated by the input pattern generator, the processing element array makes a correlating comparison, and outputs the results of the correlating comparison to the boundary processing element, so as to acquire the decoding results required by the Comma-Free Reed-Solomon code. The results indicate the frame boundary and scrambling code groups of the cell search in a wideband code division multiple access system.

摘要翻译： 一种适用于宽带码分多址系统中的小区搜索的基于收缩阵列架构的无逗号里德 - 索罗门解码电路，更具体地说，在其电路结构中采用收缩阵列的解码电路。 用于解码电路的收缩阵列包括输入图案生成器，以心轴阵列和边界处理元件阵列的形式设计的处理元件阵列。 给定收缩阵列所需的偏斜形式输出结果并由输入模式发生器产生，处理单元阵列进行相关比较，并将相关比较的结果输出到边界处理单元，以获得解码结果 所需的免费Reed-Solomon码。 结果表明宽带码分多址系统中小区搜索的帧边界和扰码组。

公开(公告)号：US20100146373A1

公开(公告)日：2010-06-10

申请号：US12423897

申请日：2009-04-15

申请人： Yuan-Sun CHU ,  Yi-Ren CHEN ,  Chia-Ying HUANG ,  Chi-Fang LI

发明人： Yuan-Sun CHU ,  Yi-Ren CHEN ,  Chia-Ying HUANG ,  Chi-Fang LI

IPC分类号： H03M13/15 ,  G06F11/10

CPC分类号： H04L1/0052 ,  H03M13/15 ,  H04L1/0057

摘要： The present invention discloses a configurable hierarchical comma-free Reed-Solomon decoding circuit and a method thereof. The design is based on an original hierarchical parallel architecture which not only completes a decoding process faster than conventional decoder, but also utilizes less hardware to perform various algorithms with less power consumed. The architecture of the present invention has higher decoding rate than the conventional systolic architecture by a cycle ratio of 22 to 94. Further, the present invention does not require the use of ROM to store 64 sets of codewords and uses logic gates less than one fourth of the logic gates than conventional systolic architecture. As a result, the circuit of the present invention occupies less area than the conventional architecture. The circuit of the present invention is also configurable for different applications, so it can always find an optimal compromise between speed and power consumption for various decoding requirements.

摘要翻译： 本发明公开了一种可配置分层无间断里德 - 索罗门解码电路及其方法。 该设计基于原始的分层并行架构，其不仅比传统解码器更快地完成解码过程，而且还利用较少的硬件来执行具有较少功耗的各种算法。 本发明的架构具有比常规收缩结构更高的解码速率，循环比为22至94.此外，本发明不需要使用ROM来存储64组码字，并且使用小于四分之一的逻辑门 的逻辑门比传统的收缩结构。 结果，本发明的电路占用的面积小于常规架构。 本发明的电路也可以针对不同的应用进行配置，因此它可以总是在各种解码要求之间找到速度和功耗之间的最佳折中。

公开(公告)号：US20080034115A1

公开(公告)日：2008-02-07

申请号：US11496548

申请日：2006-08-01

申请人： Yuan-Sun Chu ,  Jia-Huang Lin ,  Yi-Mao Hsiao

发明人： Yuan-Sun Chu ,  Jia-Huang Lin ,  Yi-Mao Hsiao

IPC分类号： G06F15/173

CPC分类号： G06F16/2255

摘要： An apparatus for handling hash collision of hash searching includes a hash table unit, a content addressable memory (CAM) and a multiplexer encoder. When the data are hashed to produce a hash index, and hash collision occurs, the data are stored into the CAM. When performing a hash search, the hash table unit and the CAM will be simultaneously looked up and the result will be found in only one period of time.

摘要翻译： 用于处理散列搜索的哈希冲突的装置包括散列表单元，内容可寻址存储器（CAM）和多路复用器编码器。 当数据被散列以产生散列索引，并且发生哈希冲突时，数据被存储到CAM中。 当执行散列搜索时，将同时查找散列表单元和CAM，并且只在一个时间段内找到结果。

公开(公告)号：US06944813B2

公开(公告)日：2005-09-13

申请号：US10120546

申请日：2002-04-12

申请人： Chi-Fang Li ,  Wern-Ho Sheen ,  Yuan-Sun Chu ,  Jan-Shin Ho ,  Yuan-Tzu Ting

发明人： Chi-Fang Li ,  Wern-Ho Sheen ,  Yuan-Sun Chu ,  Jan-Shin Ho ,  Yuan-Tzu Ting

IPC分类号： H03M13/15

CPC分类号： H03M13/15

摘要： A weighted decoding method and circuits for Comma-Free Reed-Solomon codes that apply to a cell search in a wideband code division multiple access system. The invention also provides a weighted decoding method wherein the decoding result of the secondary synchronization code is used as a weight for received Comma-Free Reed-Solomon symbol data, and the weighted symbol data is input to the processing element array of the decoding circuit, so as to perform a weighted correlating comparison and thus enhance the accuracy of the decoding result. The weighted decoding method put forward by the invention may apply to a decoding architecture that is based on a systolic array and the decoding architecture that is based on a folding systolic array.

摘要翻译： 一种适用于宽带码分多址系统中的小区搜索的无逗号里德 - 所罗门码的加权解码方法和电路。 本发明还提供一种加权解码方法，其中将辅同步码的解码结果用作接收到的无逗点里德 - 索洛蒙符号数据的权重，并将加权符号数据输入到解码电路的处理元件阵列， 从而进行加权相关比较，从而提高解码结果的准确性。 本发明提出的加权解码方法可以应用于基于收缩阵列和基于折叠式心脏收缩阵列的解码架构的解码架构。