公开(公告)号：US06933730B2

公开(公告)日：2005-08-23

申请号：US10683693

申请日：2003-10-09

申请人： Kenneth P. Parker ,  Jacob L. Bell

发明人： Kenneth P. Parker ,  Jacob L. Bell

IPC分类号： G01R13/02 ,  G01R13/28 ,  G01R31/02 ,  G01R31/04 ,  G01R31/26 ,  G01R31/28 ,  G01R31/312

CPC分类号： G01R31/2853 ,  G01R31/2896 ,  G01R31/312

摘要： A device for testing continuity of electrical paths through a connector of a circuit assembly has a package containing incomplete or no mission circuitry for the circuit assembly. The package is provided with a plurality of contacts for mating to a plurality of contacts of the connector. A test sensor port is integrated with the package. A plurality of passive circuit components are integrated with the package, ones of which are coupled in parallel between ones of the contacts on the package and the test sensor port.

摘要翻译： 用于测试通过电路组件的连接器的电路径的连续性的装置具有包含用于电路组件的不完整或没有任务电路的封装。 该封装设置有多个用于与连接器的多个触头配合的触点。 测试传感器端口与封装集成在一起。 多个无源电路部件与封装集成在一起，其中的一个被并联耦合在封装上的触点之间和测试传感器端口上。

公开(公告)号：US07411407B2

公开(公告)日：2008-08-12

申请号：US11581203

申请日：2006-10-13

申请人： Jeffrey R. Rearick ,  Jacob L. Bell

发明人： Jeffrey R. Rearick ,  Jacob L. Bell

IPC分类号： G01R27/08

CPC分类号： G01R31/2818 ,  G01R31/31712

摘要： A test system includes a circuit assembly having an IC and an external circuit. The IC includes test circuitry used to observe data indicative of target resistances in the external circuit. The test system evaluates the data to determine target resistance values. A first embodiment measures two output voltages responsive to a time varying reference voltage. The two output voltages can be used to determine resistance values in the external circuit. A second embodiment enables logic contention on the IC, controllably fixes a pull-down element on the IC, and controllably sweeps a pull-up element on the IC until the voltage at a node between the pull-down and pull-up elements and coupled to an external circuit exceeds a reference voltage.

摘要翻译： 测试系统包括具有IC和外部电路的电路组件。 该IC包括用于观察表示外部电路中的目标电阻的数据的测试电路。 测试系统评估数据以确定目标电阻值。 第一实施例测量响应于时变参考电压的两个输出电压。 两个输出电压可用于确定外部电路中的电阻值。 第二个实施例使得IC上的逻辑争用可控地固定在IC上的下拉元件，并且可控地扫描IC上的上拉元件，直到在下拉和上拉元件之间的节点处的电压并耦合 到外部电路超过参考电压。

公开(公告)号：US07170298B2

公开(公告)日：2007-01-30

申请号：US11175783

申请日：2005-07-05

申请人： Kenneth P. Parker ,  Jacob L. Bell

发明人： Kenneth P. Parker ,  Jacob L. Bell

IPC分类号： G01R31/04 ,  G01R31/02

CPC分类号： G01R31/2853 ,  G01R31/2896 ,  G01R31/312

摘要： In one embodiment, a method for testing continuity of electrical paths through a circuit assembly includes: 1) mating a test-facilitating circuit package to a connector of the circuit assembly; the circuit package having a plurality of contacts for mating to a plurality of contacts of the connector; the circuit package containing incomplete or no mission circuitry for the circuit assembly, but containing a plurality of passive circuit components coupled in parallel between the package's plurality of contacts and a test sensor port of the circuit package; 2) stimulating one or more nodes of the circuit assembly; 3) measuring an electrical characteristic of the circuit package; and 4) comparing the measured electrical characteristic to at least one threshold to assess continuities of at least two electrical paths through the circuit assembly. Other embodiments are also disclosed.

摘要翻译： 在一个实施例中，一种用于测试通过电路组件的电路径的连续性的方法包括：1）将测试促进电路封装与电路组件的连接器相配合; 所述电路封装具有用于与所述连接器的多个触点配合的多个触点; 所述电路封装包含用于所述电路组件的不完整或没有任务电路，但是包含并联在所述封装的多个触点之间的多个无源电路部件和所述电路封装的测试传感器端口; 2）刺激电路组件的一个或多个节点; 3）测量电路封装的电气特性; 以及4）将测量的电特性与至少一个阈值进行比较，以评估通过电路组件的至少两个电路径的连续性。 还公开了其他实施例。

公开(公告)号：US06233104B1

公开(公告)日：2001-05-15

申请号：US09294239

申请日：1999-04-19

申请人： Jacob L. Bell

发明人： Jacob L. Bell

IPC分类号： G11B2504

CPC分类号： G06K7/084

摘要： A magnetic strip interface reads data from a first track and a second track of a magnetic strip. The magnetic strip interface transmits the data read from the first track to a first data handler, which converts this data into a first data word, and the magnetic strip interface also transmits the data read from the second track to a second data handler, which converts this data into a second data word. The first and second data handlers transmit the first and second data words, respectively, to a multiplexer in response to command signals transmitted from a control mechanism. The multiplexer transmits the first and second data words received from the first and second data handlers, respectively, in response to control signals transmitted from the control mechanism. The control mechanism analyzes a priority scheme to determine the timing of transmissions from the data handlers.

摘要翻译： 磁条接口从磁条的第一轨道和第二轨道读取数据。 磁条接口将从第一轨道读取的数据传送到第一数据处理器，该第一数据处理器将该数据转换为第一数据字，并且磁条接口还将从第二轨道读取的数据传送到第二数据处理器， 该数据转换成第二数据字。 第一和第二数据处理器响应于从控制机制发送的命令信号，分别将第一和第二数据字发送到复用器。 复用器响应于从控制机构发送的控制信号，分别发送从第一和第二数据处理器接收的第一和第二数据字。 控制机制分析优先级方案以确定来自数据处理程序的传输的定时。

公开(公告)号：US6049478A

公开(公告)日：2000-04-11

申请号：US262405

申请日：1999-03-04

申请人： Thomas M Walley ,  Jacob L. Bell ,  William L. Pherigo, Jr.

发明人： Thomas M Walley ,  Jacob L. Bell ,  William L. Pherigo, Jr.

IPC分类号： G06K17/00 ,  G06K7/016 ,  G06K7/08 ,  G11B5/02 ,  G11B5/09 ,  G11B20/10 ,  G11C7/00

CPC分类号： G06K7/084 ,  G06K7/016

摘要： Disclosed is a system and method for generating a data sequence from a two frequency coherent phase signal. The system comprises an integrated magnetic read channel that includes a magnetic reader circuit configured to generate an analog two frequency coherent phase (F2F) signal from a magnetic strip, the analog F2F signal having a number of alternating positive and negative peaks having a respective positive and negative transitions therebetween. The output of the magnetic reader circuit is applied to an analog-to-digital converter configured to convert the analog F2F signal into a digital F2F signal. Thereafter, the digital F2F signal is applied to a peak detector configured to identify the alternating negative and positive peaks. The magnetic read channel also includes a transition calculator configured to determine a transition time between each of the consecutively positioned alternating positive and negative peaks, and a frequency locked loop configured to determine a transition type for each of the transition times. Finally, the output of the frequency locked loop is applied to a data separator configured to determine a data value from the transition types.

摘要翻译： 公开了一种用于从双频相干相位信号产生数据序列的系统和方法。 该系统包括集成磁读取通道，其包括被配置为从磁条产生模拟两相位相位相位（F2F）信号的磁读取器电路，模拟F2F信号具有多个交替的正和负峰值，其具有相应的正和 其间的负变换。 磁读取器电路的输出被应用于被配置为将模拟F2F信号转换为数字F2F信号的模拟 - 数字转换器。 此后，数字F2F信号被施加到配置成识别交替的负峰值和正峰值的峰值检测器。 磁读取通道还包括转移计算器，其被配置为确定每个连续定位的交替正和负峰值之间的转换时间，以及被配置为确定每个转换时间的转换类型的频率锁定回路。 最后，频率锁定循环的输出被应用于配置为从转换类型确定数据值的数据分离器。