公开(公告)号：US20090237107A1

公开(公告)日：2009-09-24

申请号：US12381431

申请日：2009-03-12

申请人： Bong-Hyun Lee ,  Jung-Yun Choi ,  Jae-Han Jeon ,  Kyung-Tae Do

发明人： Bong-Hyun Lee ,  Jung-Yun Choi ,  Jae-Han Jeon ,  Kyung-Tae Do

IPC分类号： H03K19/003 ,  H04B15/00

CPC分类号： H04B15/02 ,  H04B2215/064

摘要： A circuit having an active clock shielding structure includes a logic circuit that receives a clock signal and performs a logic operation based on the clock signal, a power gating circuit that switches a mode of the logic circuit between an active mode and an sleep mode based on a power gating signal, a clock signal transmission line that transmits the clock signal to the logic circuit, and at least one power gating signal transmission line that transmits the power gating signal to the power gating circuit and functions as a shielding line pair with the clock signal transmission line.

摘要翻译： 具有有源时钟屏蔽结构的电路包括接收时钟信号并基于时钟信号执行逻辑运算的逻辑电路，基于时钟信号切换逻辑电路的模式的功率门控电路，基于 电源门控信号，将时钟信号发送到逻辑电路的时钟信号传输线，以及至少一个电源门控信号传输线，其将电源门控信号发送到电源门控电路并用作与时钟的屏蔽线对 信号传输线。

公开(公告)号：US20130069690A1

公开(公告)日：2013-03-21

申请号：US13603878

申请日：2012-09-05

申请人： Hyung Ock KIM ,  Jae Han JEON ,  Jung Yun CHOI ,  Hyo Sig WON ,  Kyu Myung CHOI

发明人： Hyung Ock KIM ,  Jae Han JEON ,  Jung Yun CHOI ,  Hyo Sig WON ,  Kyu Myung CHOI

IPC分类号： H03K17/16

CPC分类号： H03K19/0016 ,  H03K19/00361 ,  Y10T307/461 ,  Y10T307/951

摘要： A power control circuit is connected between a power supply voltage and a logic circuit to switch power supplied to the logic circuit. The power control circuit includes a plurality of first power gating cells (PGCs) receiving an external mode change signal in parallel, at least one second PGC connected with one first PGC, at least one third PGC connected with the at least one second PGC, and at least one fourth PGC connected with the at least one third PGC. The second power gating cell, the third PGC, and/or the fourth PGC may include a plurality of gating cells. At least one of the second, third, and fourth pluralities has power gating cells connected in series. Each of the first through fourth PGCs switches power supplied in response to the mode change signal.

摘要翻译： 功率控制电路连接在电源电压和逻辑电路之间，以切换提供给逻辑电路的电力。 功率控制电路包括并联接收外部模式改变信号的多个第一功率门控单元（PGC），与一个第一PGC连接的至少一个第二PGC，与至少一个第二PGC连接的至少一个第三PGC，以及 与所述至少一个第三PGC连接的至少一个第四PGC。 第二电源门控单元，第三PGC和/或第四PGC可以包括多个门控单元。 第二，第三和第四多个中的至少一个具有串联连接的电力门控单元。 第一至第四PGC中的每一个响应于模式改变信号而切换供电。

公开(公告)号：US08522188B2

公开(公告)日：2013-08-27

申请号：US13626121

申请日：2012-09-25

申请人： Hyung-Ock Kim ,  Jae-Han Jeon ,  Jung-Yun Choi ,  Kee-Sup Kim ,  Hyo-Sig Won

发明人： Hyung-Ock Kim ,  Jae-Han Jeon ,  Jung-Yun Choi ,  Kee-Sup Kim ,  Hyo-Sig Won

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/5045 ,  G06F2217/84 ,  H01L27/0207

摘要： In a method of designing a system-on-chip including a tapless standard cell to which body biasing is applied, a slow corner timing parameter is adjusted to increase a slow corner of an operating speed distribution for the system-on-chip by reflecting forward body biasing, and a fast corner timing parameter is adjusted to decrease a fast corner of the operating speed distribution for the system-on-chip by reflecting reverse body biasing. The system-on-chip including the tapless standard cell is implemented based on the adjusted slow corner timing parameter corresponding to the increased slow corner and the adjusted fast corner timing parameter corresponding to the decreased fast corner. The slow corner timing parameter corresponds to a lowest value of an operating speed design window of the system-on-chip, and, the fast corner timing parameter corresponds to a highest value of the operating speed design window of the system-on-chip.

摘要翻译： 在设计片上系统的方法中，包括应用了身体偏置的无电话标准单元，通过反转向前的方式，调整慢转角定时参数以增加片上系统的运行速度分布的缓慢的转角 主体偏置和快速转角定时参数被调整，以通过反射反向主体偏置来减小片上系统的运行速度分布的快速转角。 基于对应于增加的慢转角的调整的慢转角定时参数和对应于减小的快速拐角的经调整的快速角定时参数，实现包括无tapless标准单元的片上系统。 慢转角定时参数对应于片上系统的运行速度设计窗口的最低值，快速转角定时参数对应于片上系统的运行速度设计窗口的最高值。

公开(公告)号：US20160322097A1

公开(公告)日：2016-11-03

申请号：US15009149

申请日：2016-01-28

申请人： In-Sub SHIN ,  Jae-Han JEON ,  Hyung-Ock KIM

发明人： In-Sub SHIN ,  Jae-Han JEON ,  Hyung-Ock KIM

IPC分类号： G11C11/417

CPC分类号： G11C11/417 ,  G11C5/14 ,  G11C5/148 ,  G11C7/1006

摘要： A system-on-chip and an electronic device including the system-on-chip are provided. The system-on-chip includes a power switch, a logic block, a memory device, and a buffer. The power switch is coupled between a first power supply line and a virtual power supply line, and turns on in response to a switch control signal. The logic block is coupled between the virtual power supply line and a ground line. The memory device is coupled between a second power supply line and the ground line. The buffer is coupled between the second power supply line and the ground line, and generates the switch control signal based on a sleep signal.

摘要翻译： 提供了片上系统和包括片上系统的电子设备。 片上系统包括电源开关，逻辑块，存储器件和缓冲器。 电源开关耦合在第一电源线和虚拟电源线之间，并且响应于开关控制信号而导通。 逻辑块耦合在虚拟电源线和地线之间。 存储器件耦合在第二电源线和接地线之间。 缓冲器耦合在第二电源线和接地线之间，并且基于睡眠信号产生开关控制信号。

公开(公告)号：US08659316B2

公开(公告)日：2014-02-25

申请号：US13603878

申请日：2012-09-05

申请人： Hyung Ock Kim ,  Jae Han Jeon ,  Jung Yun Choi ,  Hyo Sig Won ,  Kyu Myung Choi

发明人： Hyung Ock Kim ,  Jae Han Jeon ,  Jung Yun Choi ,  Hyo Sig Won ,  Kyu Myung Choi

IPC分类号： H03K17/16 ,  H03K19/003 ,  H02J3/14 ,  H01H35/00

CPC分类号： H03K19/0016 ,  H03K19/00361 ,  Y10T307/461 ,  Y10T307/951

摘要： A power control circuit is connected between a power supply voltage and a logic circuit to switch power supplied to the logic circuit. The power control circuit includes a plurality of first power gating cells (PGCs) receiving an external mode change signal in parallel, at least one second PGC connected with one first PGC, at least one third PGC connected with the at least one second PGC, and at least one fourth PGC connected with the at least one third PGC. The second power gating cell, the third PGC, and/or the fourth PGC may include a plurality of gating cells. At least one of the second, third, and fourth pluralities has power gating cells connected in series. Each of the first through fourth PGCs switches power supplied in response to the mode change signal.

摘要翻译： 功率控制电路连接在电源电压和逻辑电路之间，以切换提供给逻辑电路的电力。 功率控制电路包括并联接收外部模式改变信号的多个第一功率门控单元（PGC），与一个第一PGC连接的至少一个第二PGC，与至少一个第二PGC连接的至少一个第三PGC，以及 与所述至少一个第三PGC连接的至少一个第四PGC。 第二电源门控单元，第三PGC和/或第四PGC可以包括多个门控单元。 第二，第三和第四多个中的至少一个具有串联连接的电力门控单元。 第一至第四PGC中的每一个响应于模式改变信号而切换供电。

公开(公告)号：US20130185692A1

公开(公告)日：2013-07-18

申请号：US13626121

申请日：2012-09-25

申请人： Hyung-Ock KIM ,  Jae-Han JEON ,  Jung-Yun CHOI ,  Kee-Sup KIM ,  Hyo-Sig WON

发明人： Hyung-Ock KIM ,  Jae-Han JEON ,  Jung-Yun CHOI ,  Kee-Sup KIM ,  Hyo-Sig WON

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/5045 ,  G06F2217/84 ,  H01L27/0207

摘要： In a method of designing a system-on-chip including a tapless standard cell to which body biasing is applied, a slow corner timing parameter is adjusted to increase a slow corner of an operating speed distribution for the system-on-chip by reflecting forward body biasing, and a fast corner timing parameter is adjusted to decrease a fast corner of the operating speed distribution for the system-on-chip by reflecting reverse body biasing. The system-on-chip including the tapless standard cell is implemented based on the adjusted slow corner timing parameter corresponding to the increased slow corner and the adjusted fast corner timing parameter corresponding to the decreased fast corner. The slow corner timing parameter corresponds to a lowest value of an operating speed design window of the system-on-chip, and, the fast corner timing parameter corresponds to a highest value of the operating speed design window of the system-on-chip.

摘要翻译： 在设计片上系统的方法中，包括应用了身体偏置的无电话标准单元，通过反转向前的方式，调整慢转角定时参数以增加片上系统的运行速度分布的缓慢的转角 主体偏置和快速转角定时参数被调整，以通过反射反向主体偏置来减小片上系统的运行速度分布的快速转角。 基于对应于增加的慢转角的调整的慢转角定时参数和对应于减小的快速拐角的经调整的快速角定时参数，实现包括无tapless标准单元的片上系统。 慢转角定时参数对应于片上系统的运行速度设计窗口的最低值，快速转角定时参数对应于片上系统的运行速度设计窗口的最高值。

公开(公告)号：US08013628B2

公开(公告)日：2011-09-06

申请号：US12381431

申请日：2009-03-12

申请人： Bong-Hyun Lee ,  Jung-Yun Choi ,  Jae-Han Jeon ,  Kyung-Tae Do

发明人： Bong-Hyun Lee ,  Jung-Yun Choi ,  Jae-Han Jeon ,  Kyung-Tae Do

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： H04B15/02 ,  H04B2215/064

摘要： A circuit having an active clock shielding structure includes a logic circuit that receives a clock signal and performs a logic operation based on the clock signal, a power gating circuit that switches a mode of the logic circuit between an active mode and an sleep mode based on a power gating signal, a clock signal transmission line that transmits the clock signal to the logic circuit, and at least one power gating signal transmission line that transmits the power gating signal to the power gating circuit and functions as a shielding line pair with the clock signal transmission line.

摘要翻译： 具有有源时钟屏蔽结构的电路包括接收时钟信号并基于时钟信号执行逻辑运算的逻辑电路，基于时钟信号切换逻辑电路的模式的功率门控电路，基于 电源门控信号，将时钟信号发送到逻辑电路的时钟信号传输线，以及至少一个电源门控信号传输线，其将电源门控信号发送到电源门控电路并用作与时钟的屏蔽线对 信号传输线。