公开(公告)号：US5849607A

公开(公告)日：1998-12-15

申请号：US598849

申请日：1996-02-09

申请人： Dong Soo Seo ,  Wan Gyun Choi ,  Young Jae Song ,  Jae Myung Park

发明人： Dong Soo Seo ,  Wan Gyun Choi ,  Young Jae Song ,  Jae Myung Park

IPC分类号： H01L21/603 ,  H01L21/56 ,  H01L21/60

CPC分类号： H01L24/80 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01077 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/181

摘要： A method for manufacturing of a lead-on-chip type semiconductor chip package is disclosed, which comprises the steps of coating a liquid polyimide coating material on the bonding faces of at least one of the inner leads and the bus bars of the lead frame and the semiconductor chip, attaching the semiconductor chip by using the cured liquid polyimide coating material as an attaching medium, and forming a package body for wrapping and protecting the semiconductor chip and bonding wires. Since the liquid polyimide coating material protects the wafer from which the chips are obtained and also serves as a bonding agent for the semiconductor chip at the same time, the semiconductor chip package according to the present invention can be protected from damage, such as by air bubbles, which are generated at the interface of the conventional polyimide tape, and by separation and expansion of adhesives. Consequently, the method is applicable to a semiconductor chip package having a thickness that is thinner than that of conventional semiconductor chip package.

摘要翻译： 公开了一种制造片上型芯片型半导体芯片封装的方法，其包括以下步骤：在引线框架的内引线和母线的至少一个的接合面上涂布液体聚酰亚胺涂层材料，以及 半导体芯片，通过使用固化的液体聚酰亚胺涂层材料作为附着介质附着半导体芯片，以及形成用于包覆和保护半导体芯片和接合线的封装体。 由于液体聚酰亚胺涂层材料保护了获得芯片的晶片，并且同时用作半导体芯片的粘结剂，因此可以保护根据本发明的半导体芯片封装件不受诸如空气的损坏 在常规聚酰亚胺胶带的界面处产生的气泡，以及粘合剂的分离和膨胀。 因此，该方法适用于厚度比现有的半导体芯片封装薄的半导体芯片封装。

公开(公告)号：US5568057A

公开(公告)日：1996-10-22

申请号：US542023

申请日：1995-10-12

申请人： Gu Sung Kim ,  Jae Myung Park

发明人： Gu Sung Kim ,  Jae Myung Park

IPC分类号： H01L21/66 ,  G01R1/04 ,  G01R31/28 ,  H01L23/32 ,  H05K7/10 ,  G01R31/02

CPC分类号： G01R31/2863 ,  G01R1/0433 ,  H05K7/103 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/92247

摘要： An apparatus for burn-in test comprising, a socket body including an accommodation groove in which an integrated circuit chip is accommodated to be tested, a step sill portion formed around the accommodation groove, a plurality of inner leads formed on the step sill portion, a plurality of outer leads protruded from the socket body and electrically connected to said inner leads through the socket body, and a supporting element attached to opposite inside walls of the accommodation groove to support the integrated circuit chip, and a method for burn-in test comprising the steps of: (a) mounting an integrated circuit chip to be tested in the accommodation groove; (b) bonding pads of the integrated circuit chip with the corresponding inner leads through a plurality of wires; (c) mounting the socket body on a test board by the outer leads and applying test pattern signals to the integrated circuit chip through the inner and outer leads in the condition of high temperature and high voltage; and (d) severing and removing the wires.

摘要翻译： 一种用于老化试验的装置，包括：插座主体，包括容纳凹槽的插座体，集成电路芯片容纳在待测试中;台阶台阶部分，围绕容纳槽形成，多个内引线形成在台阶台阶上， 多个从所述插座主体突出并且通过所述插座体电连接到所述内部引线的外部引线，以及附接到所述容纳槽的相对的内壁以支撑所述集成电路芯片的支撑元件，以及用于老化测试的方法 包括以下步骤：（a）将待测试的集成电路芯片安装在容纳槽中; （b）集成电路芯片的接合焊盘与相应的内引线通过多根导线; （c）通过外引线将插座主体安装在测试板上，并在高温高压条件下通过内引线和外引线将测试图形信号施加到集成电路芯片; 和（d）切断和除去电线。