公开(公告)号：US5898325A

公开(公告)日：1999-04-27

申请号：US895717

申请日：1997-07-17

Applicant: David T. Crook ,  Thomas E. Tice ,  James A. Surber, Jr.

Inventor： David T. Crook ,  Thomas E. Tice ,  James A. Surber, Jr.

IPC: H03B21/00 ,  H03L7/18

CPC classification number: H03B21/00 ,  G06F1/0328

Abstract: A dual-tunable direct digital synthesizer is provided with a programmable frequency multiplier that multiplies a relatively low frequency fixed clock signal F.sub.clk so that the output frequency F.sub.o of the waveform is:F.sub.o =(F.sub.n /2.sup.N).times.(M.times.F.sub.clk)where N is the resolution of the digital control word, the tuning word F.sub.n is the value of the N-bit control word, M is the multiplication factor and M*F.sub.clk is the DDS clock frequency. The multiplication factor and, hence, the DDS clock can be reduced to track changes in the output frequency thereby lowering the average power consumption. Because the synthesizer can generate the same output frequency using different tuning word-to-DDS clock ratios, it can be tuned for optimum SFDR over a narrow band around the desired output frequency. In other words, an "enhanced dynamic range band" in the harmonic and spurious performance can be mapped out for each frequency in the bandwidth.

Abstract translation: 双调谐直接数字合成器具有可编程倍频器，其将相对低频的固定时钟信号Fclk相乘，使得波形的输出频率Fo为：Fo =（Fn / 2N）×（MxFclk）其中N为 数字控制字的分辨率，调谐字Fn是N位控制字的值，M是乘法因子，M * Fclk是DDS时钟频率。 因此，可以减少乘法因子和DDS时钟以跟踪输出频率的变化，从而降低平均功耗。 由于合成器可以使用不同的调谐字DDS时钟比产生相同的输出频率，因此可以针对所需输出频率周围的窄带调节最佳SFDR。 换句话说，可以为带宽中的每个频率映射谐波和杂散性能中的“增强型动态范围带”。