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1.发明授权Dual tunable direct digital synthesizer with a frequency programmable clock and method of tuning 失效具有频率可编程时钟和调谐方式的双可调直接数字合成器
公开(公告)号：US5898325A
公开(公告)日：1999-04-27
申请号：US895717
申请日：1997-07-17
CPC分类号： H03B21/00 , G06F1/0328
摘要： A dual-tunable direct digital synthesizer is provided with a programmable frequency multiplier that multiplies a relatively low frequency fixed clock signal F.sub.clk so that the output frequency F.sub.o of the waveform is:F.sub.o =(F.sub.n /2.sup.N).times.(M.times.F.sub.clk)where N is the resolution of the digital control word, the tuning word F.sub.n is the value of the N-bit control word, M is the multiplication factor and M*F.sub.clk is the DDS clock frequency. The multiplication factor and, hence, the DDS clock can be reduced to track changes in the output frequency thereby lowering the average power consumption. Because the synthesizer can generate the same output frequency using different tuning word-to-DDS clock ratios, it can be tuned for optimum SFDR over a narrow band around the desired output frequency. In other words, an "enhanced dynamic range band" in the harmonic and spurious performance can be mapped out for each frequency in the bandwidth.
摘要翻译： 双调谐直接数字合成器具有可编程倍频器，其将相对低频的固定时钟信号Fclk相乘，使得波形的输出频率Fo为：Fo =（Fn / 2N）×（MxFclk）其中N为 数字控制字的分辨率，调谐字Fn是N位控制字的值，M是乘法因子，M * Fclk是DDS时钟频率。 因此，可以减少乘法因子和DDS时钟以跟踪输出频率的变化，从而降低平均功耗。 由于合成器可以使用不同的调谐字DDS时钟比产生相同的输出频率，因此可以针对所需输出频率周围的窄带调节最佳SFDR。 换句话说，可以为带宽中的每个频率映射谐波和杂散性能中的“增强型动态范围带”。
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2.发明授权High speed active overvoltage detection and protection for overvoltage sensitive circuits 失效用于过电压敏感电路的高速有源过压检测和保护
公开(公告)号：US5479119A
公开(公告)日：1995-12-26
申请号：US344452
申请日：1994-11-23
摘要： An overvoltage protection circuit protects against saturation and damage of sensitive circuitry elements. The protection circuit includes an out-of-range detector which compares an input signal to reference levels to determine if it is within a predetermined range of acceptable inputs. If the input is determined not to be within this range, a control circuit substitutes a supplemental signal within the range for the input signal. Digital correction can be provided to correct the output of the sensitive circuit element while the supplemental signal is being substituted. Numerous circuit designs may be used to implement the protection scheme.
摘要翻译： 过压保护电路可以防止敏感电路元件的饱和和损坏。 保护电路包括超出范围检测器，其将输入信号与参考电平进行比较，以确定其是否在可接受输入的预定范围内。 如果确定输入不在该范围内，则控制电路将输入信号范围内的补充信号代入。 可以提供数字校正以在补充信号被替代时校正敏感电路元件的输出。 可以使用许多电路设计来实现保护方案。
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公开(公告)号：US5661422A
公开(公告)日：1997-08-26
申请号：US571243
申请日：1995-12-12
摘要： A protection circuit inhibits saturation and damage of sensitive circuit elements when an input signal goes out of a nominal input range. The protection circuit includes an out-of-range detector which compares the input signal to reference levels to determine if it is within the range. If it is not, a control circuit substitutes a supplemental signal that is slightly out of range, but not so far out of range as to cause any substantial saturation. Supplemental signal sources that produce supplemental signals slightly outside the high and low ends of the range with error margins, not more than about 750 mV, that lie just outside the range; an out-of-range input is replaced by the supplemental signal with the closest value. The invention is particularly applicable to multistep/subranging analog-to-digital/converters.
摘要翻译： 当输入信号超出标称输入范围时，保护电路可以抑制敏感电路元件的饱和和损坏。 保护电路包括超出范围的检测器，其将输入信号与参考电平进行比较，以确定其是否在该范围内。 如果不是这样，则控制电路将稍微超出范围的补充信号代替，但是不能超出范围，导致任何显着的饱和。 补充信号源产生稍微超出范围的高端和低端的补充信号，误差范围不大于约750mV，处于范围之外; 超范围输入由具有最接近的值的补充信号代替。 本发明特别适用于模数转换器的多级/次级化。
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4.发明授权Differential amplifiers which can form a residue amplifier in sub-ranging A/D converters 失效差分放大器可在子范围A / D转换器中形成残留放大器
公开(公告)号：US5530444A
公开(公告)日：1996-06-25
申请号：US368862
申请日：1995-01-05
CPC分类号： H03F3/45098 , H03F1/083 , H03F3/45085 , H03F2203/45392 , H03F2203/45702 , H03F2203/45722 , H03F2203/5003 , H03M1/16
摘要： Open-loop differential amplifiers (120, 140) are disclosed which have accurate and stable gain. The gain of these amplifiers is substantially insensitive to the effects of small-signal emitter resistance r.sub.e, current gain .beta. and Early voltage V.sub.A. Thus, their gain can be accurately set by resistance ratios which makes them particularly useful in integrated circuits. These advantages are obtained with an output differential pair (67) that has cross-coupled base and collector terminals. In addition, resistors (141, 143, 148, 150) and a current source (146) associated with this differential pair are related to like elements (27, 28, 24, 25 and 26) that are associated with an input differential pair (21) by disclosed numerical ratios, e.g., the nominal gain G of the amplifier. Versions of the amplifiers can be adapted for use as a residue amplifier (162) in a subranging A/D converter (160).
摘要翻译： 公开了具有准确和稳定增益的开环差分放大器（120,140）。 这些放大器的增益对小信号发射极电阻re，电流增益β和早期电压VA的影响基本上不敏感。 因此，它们的增益可以通过电阻比来精确地设定，这使得它们在集成电路中特别有用。 这些优点通过具有交叉耦合基极和集电极端子的输出差分对（67）获得。 另外，与该差分对相关联的电阻（141,143,148,150）和电流源（146）与与输入差分对相关联的相似元件（27,28,24,25和26）有关 21）通过公开的数值比例，例如放大器的标称增益G。 放大器的版本可以适用于在亚排A / D转换器（160）中的残留放大器（162）。
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公开(公告)号：US5706008A
公开(公告)日：1998-01-06
申请号：US609651
申请日：1996-03-01
CPC分类号： H03M1/0682 , H03M1/363
摘要： A new differential ladder/comparator circuit reduces settling time delays in parallel analog to digital converters. A parallel analog-to-digital converter (ADC) includes a pair of differential resistor ladders having their taps connected to a group of comparators. The comparators produce digital "thermometer" scale outputs corresponding to analog signals impressed upon the differential ladders. By employing double-value resistors to form the "rungs" of the ladders and by connecting the comparators to the ladder taps in a way that increases the number of comparator inputs connected to the ladders' lower-order taps and decreases the number of comparator inputs connected to the ladders' higher order taps, the input impedance presented by the ladder/comparator combination is reduced in comparison with conventional differential ladder parallel ADCs. Additionally, input signals are superimposed upon the ladders by drivers which, in a preferred embodiment, present lower output impedances to the ladders than prior art drivers, further improving the bandwidth of the ADC.
摘要翻译： 新的差分梯形图/比较器电路减少并行模数转换器的稳定时间延迟。 并行模数转换器（ADC）包括一对具有连接到一组比较器的抽头的差分电阻梯。 比较器产生对应于印在差分梯子上的模拟信号的数字“温度计”刻度输出。 通过采用双值电阻器来形成梯子的“梯级”，并通过将比较器连接到梯形抽头，以增加连接到梯级低阶抽头的比较器输入的数量并减少比较器输入的数量 连接到梯子的高阶抽头，与传统的差分梯形并行ADC相比，梯形图/比较器组合所呈现的输入阻抗减小。 此外，输入信号通过驱动器叠加在梯子上，在优选实施例中，驱动器向梯子提供比现有技术驱动器更低的输出阻抗，进一步提高了ADC的带宽。
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公开(公告)号：US4940980A
公开(公告)日：1990-07-10
申请号：US348050
申请日：1989-05-05
申请人： Thomas E. Tice
发明人： Thomas E. Tice
CPC分类号： H03M1/0604 , H03M1/36
摘要： A flash converter in which an input circuit is provided for maintaining a substantially constant collector-base voltage on the input emitter-followers, so as to obviate the distortion caused by variation of the input capacitance with input voltage. The driving source directly drives the base of the emitter-followers and, through a level-shift circuit, also drives the collectors of the emitter-follower transistors.
摘要翻译： 一种闪存转换器，其中提供输入电路用于在输入发射极跟随器上保持基本上恒定的集电极基极电压，以便消除由输入电容与输入电压的变化引起的失真。 驱动源直接驱动发射极跟随器的基极，并且通过电平移位电路也驱动发射极跟随器晶体管的集电极。
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