公开(公告)号：US20060107243A1

公开(公告)日：2006-05-18

申请号：US10992031

申请日：2004-11-18

申请人： James Chlipala ,  Shahriar Moinian

发明人： James Chlipala ,  Shahriar Moinian

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  H01L21/76224 ,  H01L27/0207

摘要： The present invention provides a method for manufacturing a semiconductor device, comprising: determining an isolation structure stress effect of a first semiconductor device, determining an optical proximity effect of a second semiconductor device, selecting a modeling design parameter such that the isolation structure stress effect is offset against the optical proximity effect on a fabrication model, and using the selected design parameter to construct a third semiconductor device.

摘要翻译： 本发明提供一种制造半导体器件的方法，包括：确定第一半导体器件的隔离结构应力效应，确定第二半导体器件的光学邻近效应，选择建模设计参数，使得隔离结构应力效应为 抵消制造模型上的光学邻近效应，并且使用所选择的设计参数来构造第三半导体器件。

公开(公告)号：US20050088958A1

公开(公告)日：2005-04-28

申请号：US10780945

申请日：2004-02-18

申请人： Christopher Abel ,  Joseph Anidjar ,  James Chlipala ,  Abhishek Duggal ,  Donald Laturell

发明人： Christopher Abel ,  Joseph Anidjar ,  James Chlipala ,  Abhishek Duggal ,  Donald Laturell

IPC分类号： G06F13/40 ,  H04B3/32 ,  H04J1/12 ,  H05K1/02

CPC分类号： G06F13/409 ,  H04B3/32 ,  H05K1/0216

摘要： A system for a backplane that employs i) an adjustment of positive-to-negative (P-N) driver skew of a transmit signal of a relatively high-speed differential driver to reduce far-end crosstalk, ii) a high-speed differential subtraction circuit combining a gain-adjusted replica of at least one transmit signal with a received signal to reduce near-end crosstalk, and iii) a phase-locked loop (PLL) synchronization circuit to align timing events between a set of near-end and far-end high-speed interfaces.

摘要翻译： 一种用于背板的系统，其采用i）调整相对高速差分驱动器的发射信号的正负（PN）驱动器偏移以减少远端串扰，ii）高速差分减法电路 将至少一个发射信号的增益调整复本与接收信号组合以减少近端串扰，以及iii）锁相环（PLL）同步电路，用于对准一组近端和远端之间的定时事件， 结束高速接口。