公开(公告)号：US20050088958A1

公开(公告)日：2005-04-28

申请号：US10780945

申请日：2004-02-18

申请人： Christopher Abel ,  Joseph Anidjar ,  James Chlipala ,  Abhishek Duggal ,  Donald Laturell

发明人： Christopher Abel ,  Joseph Anidjar ,  James Chlipala ,  Abhishek Duggal ,  Donald Laturell

IPC分类号： G06F13/40 ,  H04B3/32 ,  H04J1/12 ,  H05K1/02

CPC分类号： G06F13/409 ,  H04B3/32 ,  H05K1/0216

摘要： A system for a backplane that employs i) an adjustment of positive-to-negative (P-N) driver skew of a transmit signal of a relatively high-speed differential driver to reduce far-end crosstalk, ii) a high-speed differential subtraction circuit combining a gain-adjusted replica of at least one transmit signal with a received signal to reduce near-end crosstalk, and iii) a phase-locked loop (PLL) synchronization circuit to align timing events between a set of near-end and far-end high-speed interfaces.

摘要翻译： 一种用于背板的系统，其采用i）调整相对高速差分驱动器的发射信号的正负（PN）驱动器偏移以减少远端串扰，ii）高速差分减法电路 将至少一个发射信号的增益调整复本与接收信号组合以减少近端串扰，以及iii）锁相环（PLL）同步电路，用于对准一组近端和远端之间的定时事件， 结束高速接口。

公开(公告)号：US07496780B2

公开(公告)日：2009-02-24

申请号：US10364763

申请日：2003-02-11

申请人： Christopher J. Abel ,  Joseph Anidjar ,  Abhishek Duggal ,  Donald R. Laturell

发明人： Christopher J. Abel ,  Joseph Anidjar ,  Abhishek Duggal ,  Donald R. Laturell

IPC分类号： G06F1/12

CPC分类号： H04J3/04 ,  H04J3/0685 ,  H04L25/14

摘要： Signal processing circuitry having parallel processing channels has clock-generation circuitry that generates (i) high-speed clock signals used to drive the channels and (ii) synchronization signals used to reset the processing of the channels. In one embodiment, the signal processing circuitry has multiple multiplexing channels arranged in one or more macrocells, each macrocell having one or more channels and a phase-locked loop (PLL) that generates a high-speed PLL clock signal and a synchronization signal for the macrocell's channels. Each channel has a counter that implements a state machine used to drive the multiplexing processing, where the state machine is reset to a specified state upon receipt of each synchronization pulse in the synchronization signal.

摘要翻译： 具有并行处理通道的信号处理电路具有产生（i）用于驱动信道的高速时钟信号和（ii）用于复位通道处理的同步信号的时钟生成电路。 在一个实施例中，信号处理电路具有布置在一个或多个宏小区中的多个复用信道，每个宏小区具有一个或多个信道，以及产生高速PLL时钟信号和同步信号的锁相环（PLL） 宏单元的渠道。 每个通道具有实现用于驱动多路复用处理的状态机的计数器，其中在接收到同步信号中的每个同步脉冲时状态机被复位到指定状态。

公开(公告)号：US07366086B2

公开(公告)日：2008-04-29

申请号：US10780945

申请日：2004-02-18

申请人： Christopher J. Abel ,  Joseph Anidjar ,  James D. Chlipala ,  Abhishek Duggal ,  Donald R. Laturell

发明人： Christopher J. Abel ,  Joseph Anidjar ,  James D. Chlipala ,  Abhishek Duggal ,  Donald R. Laturell

IPC分类号： H04J1/12

CPC分类号： G06F13/409 ,  H04B3/32 ,  H05K1/0216

摘要： A system for a backplane that employs i) an adjustment of positive-to-negative (P-N) driver skew of a transmit signal of a relatively high-speed differential driver to reduce far-end crosstalk, ii) a high-speed differential subtraction circuit combining a gain-adjusted replica of at least one transmit signal with a received signal to reduce near-end crosstalk, and iii) a phase-locked loop (PLL) synchronization circuit to align timing events between a set of near-end and far-end high-speed interfaces.

摘要翻译： 一种用于背板的系统，其采用i）调整相对高速差分驱动器的发射信号的正负（PN）驱动器偏移以减少远端串扰，ii）高速差分减法电路 将至少一个发射信号的增益调整复本与接收信号组合以减少近端串扰，以及iii）锁相环（PLL）同步电路，用于对准一组近端和远端之间的定时事件， 结束高速接口。

公开(公告)号：US20070217558A1

公开(公告)日：2007-09-20

申请号：US11375828

申请日：2006-03-15

申请人： Christopher Abel ,  Joseph Anidjar ,  Vladimir Sindalovsky ,  Craig Ziemer

发明人： Christopher Abel ,  Joseph Anidjar ,  Vladimir Sindalovsky ,  Craig Ziemer

IPC分类号： H04L7/00

CPC分类号： H04L7/0008

摘要： Disclosed is a system and method for improving the linearity of a clock and data recovery (CDR) circuit. A data stream is received and the phase of a clock signal is adjusted using two interpolators. The data stream is then recovered using the clock signal.

摘要翻译： 公开了一种用于提高时钟和数据恢复（CDR）电路的线性度的系统和方法。 接收数据流，并使用两个内插器调整时钟信号的相位。 然后使用时钟信号恢复数据流。

公开(公告)号：US08385493B2

公开(公告)日：2013-02-26

申请号：US12755522

申请日：2010-04-07

申请人： Christopher Abel ,  Joseph Anidjar ,  Vladimir Sindalovsky ,  Craig Ziemer

发明人： Christopher Abel ,  Joseph Anidjar ,  Vladimir Sindalovsky ,  Craig Ziemer

IPC分类号： H04L7/02

CPC分类号： H04L7/0008

摘要： Disclosed is a system and method for improving the linearity of a clock and data recovery (CDR) circuit. In one embodiment, a data stream is received, and the phase of a clock signal is adjusted using two interpolators. The phase of the output signal of the second interpolator is adjusted simultaneously with, and complementary to, adjusting the phase of the first interpolator. The first interpolator's output signal is injected into a first delay cell in a delay loop having a plurality of delay cells, and the output of the second interpolator is inactivated. When the maximum phase of the first interpolator's output signal is reached, the second interpolator's output signal is injected into another one of the delay cells, and the first interpolator's output signal is inactivated. The data stream is then recovered using the output of the delay loop as a clock signal.

摘要翻译： 公开了一种用于提高时钟和数据恢复（CDR）电路的线性度的系统和方法。 在一个实施例中，接收数据流，并且使用两个内插器调整时钟信号的相位。 第二内插器的输出信号的相位与调整第一内插器的相位同时调整并补充。 第一内插器的输出信号被注入到具有多个延迟单元的延迟环中的第一延迟单元中，并且第二内插器的输出被非激活。 当达到第一内插器的输出信号的最大相位时，第二内插器的输出信号被注入另一个延迟单元，并且第一内插器的输出信号被去激活。 然后使用延迟环路的输出作为时钟信号来恢复数据流。

公开(公告)号：US20100195777A1

公开(公告)日：2010-08-05

申请号：US12755522

申请日：2010-04-07

申请人： Christopher Abel ,  Joseph Anidjar ,  Vladimir Sindalovsky ,  Craig Ziemer

发明人： Christopher Abel ,  Joseph Anidjar ,  Vladimir Sindalovsky ,  Craig Ziemer

IPC分类号： H04L7/033

CPC分类号： H04L7/0008

摘要： Disclosed is a system and method for improving the linearity of a clock and data recovery (CDR) circuit. In one embodiment, a data stream is received, and the phase of a clock signal is adjusted using two interpolators. The phase of the output signal of the second interpolator is adjusted simultaneously with, and complementary to, adjusting the phase of the first interpolator. The first interpolator's output signal is injected into a first delay cell in a delay loop having a plurality of delay cells, and the output of the second interpolator is inactivated. When the maximum phase of the first interpolator's output signal is reached, the second interpolator's output signal is injected into another one of the delay cells, and the first interpolator's output signal is inactivated. The data stream is then recovered using the output of the delay loop as a clock signal.

摘要翻译： 公开了一种用于提高时钟和数据恢复（CDR）电路的线性度的系统和方法。 在一个实施例中，接收数据流，并且使用两个内插器调整时钟信号的相位。 第二内插器的输出信号的相位与调整第一内插器的相位同时调整并补充。 第一内插器的输出信号被注入到具有多个延迟单元的延迟环中的第一延迟单元中，并且第二内插器的输出被去激活。 当达到第一内插器的输出信号的最大相位时，第二内插器的输出信号被注入另一个延迟单元，并且第一内插器的输出信号被去激活。 然后使用延迟环路的输出作为时钟信号来恢复数据流。

公开(公告)号：US07724857B2

公开(公告)日：2010-05-25

申请号：US11375828

申请日：2006-03-15

申请人： Christopher Abel ,  Joseph Anidjar ,  Vladimir Sindalovsky ,  Craig Ziemer

发明人： Christopher Abel ,  Joseph Anidjar ,  Vladimir Sindalovsky ,  Craig Ziemer

IPC分类号： H04L7/00

CPC分类号： H04L7/0008

摘要： Disclosed is a system and method for improving the linearity of a clock and data recovery (CDR) circuit. In one embodiment, a data stream is received, and the phase of a clock signal is adjusted using two interpolators. The phase of the output signal of the second interpolator is adjusted simultaneously with, and complementary to, adjusting the phase of the first interpolator. The first interpolator's output signal is injected into a first delay cell in a delay loop having a plurality of delay cells, and the output of the second interpolator is inactivated. When the maximum phase of the first interpolator's output signal is reached, the second interpolator's output signal is injected into another one of the delay cells, and the first interpolator's output signal is inactivated. The data stream is then recovered using the output of the delay loop as a clock signal.

摘要翻译： 公开了一种用于提高时钟和数据恢复（CDR）电路的线性度的系统和方法。 在一个实施例中，接收数据流，并且使用两个内插器调整时钟信号的相位。 第二内插器的输出信号的相位与调整第一内插器的相位同时调整并补充。 第一内插器的输出信号被注入到具有多个延迟单元的延迟环中的第一延迟单元中，并且第二内插器的输出被非激活。 当达到第一内插器的输出信号的最大相位时，第二内插器的输出信号被注入另一个延迟单元，并且第一内插器的输出信号被去激活。 然后使用延迟环路的输出作为时钟信号来恢复数据流。

公开(公告)号：US20090212856A1

公开(公告)日：2009-08-27

申请号：US12437860

申请日：2009-05-08

申请人： Jinghong Chen ,  Gregory W. Sheets ,  Joseph Anidjar ,  Robert J. Kapuschinsky ,  Lane A. Smith

发明人： Jinghong Chen ,  Gregory W. Sheets ,  Joseph Anidjar ,  Robert J. Kapuschinsky ,  Lane A. Smith

IPC分类号： H03F1/02

CPC分类号： H03F3/45973 ,  H03F3/45977 ,  H03F2203/45101 ,  H03F2203/45434 ,  H03F2203/45564 ,  H03F2203/45588 ,  H03F2203/45622

摘要： An amplifier having DC offset compensation includes at least one input node and a pair of differential output nodes, a biasing circuit coupled to the input node; and a plurality of current sources. Selected ones of said current sources are coupled to the input node to adjust a DC voltage at the input node to provide DC offset compensation for the amplifier

摘要翻译： 具有DC偏移补偿的放大器包括至少一个输入节点和一对差分输出节点，偏置电路耦合到输入节点; 和多个电流源。 所选择的所述电流源耦合到输入节点以调整输入节点处的DC电压，以为放大器提供DC偏移补偿

公开(公告)号：US20100244937A1

公开(公告)日：2010-09-30

申请号：US12160373

申请日：2007-10-31

申请人： Joseph Anidjar ,  Mohammad S. Mobin ,  Gregory W. Sheets ,  Vladimir Sindalovsky ,  Lane A. Smith

发明人： Joseph Anidjar ,  Mohammad S. Mobin ,  Gregory W. Sheets ,  Vladimir Sindalovsky ,  Lane A. Smith

IPC分类号： G05F1/10

CPC分类号： H03K19/00369

摘要： A compensation circuit for reducing power consumption in at least one digital circuit includes a first sample circuit connected to a first supply voltage, a second sample circuit connected to a second supply voltage, and a controller connected to the first and second sample circuits. The first and second sample circuits are substantially functionally equivalent to one another but optimized for different regions of operation within a specified range of PVT conditions. The controller is operative to receive respective output signals from the first and second sample circuits, to monitor a functionality of the second sample circuit relative to the first sample circuit, and to adjust a level of the second supply voltage to ensure correct operation of the second sample circuit throughout the specified range of PVT conditions. The digital circuit is operative from the second supply voltage.

摘要翻译： 用于降低至少一个数字电路中的功耗的补偿电路包括连接到第一电源电压的第一采样电路，连接到第二电源电压的第二采样电路和连接到第一和第二采样电路的控制器。 第一和第二采样电路基本上在功能上彼此相等，但是在PVT条件的指定范围内针对不同操作区域进行了优化。 控制器可操作以从第一和第二采样电路接收相应的输出信号，以监测第二采样电路相对于第一采样电路的功能，并调整第二电源电压的电平，以确保第二采样电路的正常工作 采样电路在指定的PVT条件范围内。 数字电路从第二电源电压工作。

公开(公告)号：US07368975B2

公开(公告)日：2008-05-06

申请号：US11376606

申请日：2006-03-15

申请人： Joseph Anidjar

发明人： Joseph Anidjar

IPC分类号： G11C5/14

CPC分类号： G11C5/147

摘要： A circuit is described that generates multiple voltages each having a common reference point. The circuit uses a feedback control loop to generate a center voltage, a first voltage generator, and a second voltage generator. The first voltage generator generates a first high voltage related to the center voltage plus a first offset voltage and a first low voltage related to the center voltage minus the first offset voltage, where the first offset voltage is determined by a first control input to the first voltage generator. The second voltage generator generates a second high voltage related to the center voltage plus a second offset voltage and a second low voltage related to the center voltage minus the second offset voltage, where the second offset voltage is determined by a second control input to the second voltage reference generator. An example is also presented where the multiple voltage generator circuit is advantageously employed in a deserializer data acquisition system.

摘要翻译： 描述了产生多个具有公共参考点的电压的电路。 电路使用反馈控制回路来产生中心电压，第一电压发生器和第二电压发生器。 第一电压发生器产生与中心电压加上第一偏移电压和与中心电压相关的第一偏移电压相关的第一低电压的第一高电压，其中第一偏移电压由第一偏移电压由第一偏移电压 电压发生器 第二电压发生器产生与中心电压加上第二偏移电压相关的第二高电压和与中心电压减去第二偏移电压相关的第二低电压，其中第二偏移电压由第二控制输入确定到第二偏移电压 电压基准发电机。 还提出了一种示例，其中多电压发生器电路有利地用于解串器数据采集系统中。