公开(公告)号：US07812749B2

公开(公告)日：2010-10-12

申请号：US12380639

申请日：2009-03-02

申请人： Christopher Abel ,  Mohammad Mobin ,  Robert Kapuschinsky ,  Lane Smith ,  Paul Tracy ,  Gregory Sheets

发明人： Christopher Abel ,  Mohammad Mobin ,  Robert Kapuschinsky ,  Lane Smith ,  Paul Tracy ,  Gregory Sheets

IPC分类号： H03M1/06

CPC分类号： H04L25/061

摘要： In described embodiments, a communication system employing, for example, clock and data recovery (CDR) detects and applies correction for DC offset in an input data stream signal, termed as “DC offset calibration”. DC offset calibration applies static calibration for DC offset in input circuits, such as an input amplifier and detection latches, without input data, and applies statistical calibration for DC offset during operation with an input data stream to correct for dynamic shifts in DC level. Such DC offset calibration employs data eye measurements of the input data stream for detection of DC offset, and applies an opposite DC offset to maintain a relatively balanced data eye during live traffic.

摘要翻译： 在所描述的实施例中，采用例如时钟和数据恢复（CDR）的通信系统在输入数据流信号中检测并应用校正DC偏移，称为“DC偏移校准”。 DC偏移校准在输入电路（如输入放大器和检测锁存器）中对直流偏移进行静态校准，无输入数据，并在输入数据流运行期间对DC偏移进行统计校准，以校正直流电平的动态偏移。 这种DC偏移校准使用用于检测DC偏移的输入数据流的数据眼睛测量，并施加相反的DC偏移以在实时业务期间维持相对平衡的数据眼睛。

公开(公告)号：US20070217558A1

公开(公告)日：2007-09-20

申请号：US11375828

申请日：2006-03-15

申请人： Christopher Abel ,  Joseph Anidjar ,  Vladimir Sindalovsky ,  Craig Ziemer

发明人： Christopher Abel ,  Joseph Anidjar ,  Vladimir Sindalovsky ,  Craig Ziemer

IPC分类号： H04L7/00

CPC分类号： H04L7/0008

摘要： Disclosed is a system and method for improving the linearity of a clock and data recovery (CDR) circuit. A data stream is received and the phase of a clock signal is adjusted using two interpolators. The data stream is then recovered using the clock signal.

摘要翻译： 公开了一种用于提高时钟和数据恢复（CDR）电路的线性度的系统和方法。 接收数据流，并使用两个内插器调整时钟信号的相位。 然后使用时钟信号恢复数据流。

公开(公告)号：US20070052463A1

公开(公告)日：2007-03-08

申请号：US11221387

申请日：2005-09-07

申请人： Christopher Abel ,  Abhishek Duggal ,  Peter Metz ,  Vladimir Sindalovsky

发明人： Christopher Abel ,  Abhishek Duggal ,  Peter Metz ,  Vladimir Sindalovsky

IPC分类号： H03L7/06

CPC分类号： H03L7/0812 ,  H03L7/089 ,  H03L7/093

摘要： Methods and apparatus are provided for sigma-delta delay control in a Delay-Locked-Loop that employs a delay line to generate a clock signal based on a reference signal. A first value is generated if a clock signal has a time lead relative to a reference signal; and a second value is generated if a clock signal has a time lag relative to a reference signal. The first and second values are accumulated to generate an N bit digital word; and the N bit digital word is reduced to an M bit digital word, where M is less than N. Thereafter, the M bit digital word can be converted to an analog bias signal. The reducing step can be performed, for example, by a sigma-delta modulator. The high frequency quantization noise generated by the sigma-delta modulator can be filtered using a low pass filter. The converting step can be performed by a digital-to-analog converter, such as a master/slave digital-to-analog converter.

摘要翻译： 提供了延迟锁定环中的Σ-Δ延迟控制的方法和装置，其采用延迟线来基于参考信号产生时钟信号。 如果时钟信号相对于参考信号具有时间导通，则产生第一值; 并且如果时钟信号相对于参考信号具有时滞，则产生第二值。 累积第一和第二值以产生N位数字字; 并将N位数字字减少为M位数字字，其中M小于N.此后，M位数字字可以转换为模拟偏置信号。 还原步骤可以由例如Σ-Δ调制器进行。 可以使用低通滤波器对由Σ-Δ调制器产生的高频量化噪声进行滤波。 转换步骤可以由诸如主/从数字模拟转换器之类的数 - 模转换器执行。

公开(公告)号：US20070210832A1

公开(公告)日：2007-09-13

申请号：US11367964

申请日：2006-03-03

申请人： Christopher Abel ,  Weiwei Mao

发明人： Christopher Abel ,  Weiwei Mao

IPC分类号： H03K19/00

CPC分类号： H03K5/01

摘要： Methods and apparatus are provided for controlling at least one of a rise time and a fall time of a signal. A plurality of time shifted clock signals are generated; and a received data signal is sampled using a plurality of parallel data paths, where each of the data paths are controlled by a corresponding one of the plurality of time shifted clock signals. The plurality of time shifted clock signals can be generated, for example, by at least one delay element. The plurality of parallel data paths can be substantially identical and comprise, for example, at least one latch or at least one flip flop. Compensation can optionally be provided for variations in, for example, process corner, supply voltage, aging and operating temperature.

摘要翻译： 提供了用于控制信号的上升时间和下降时间中的至少一个的方法和装置。 产生多个时移信号; 并且使用多个并行数据路径对接收的数据信号进行采样，其中每个数据路径由多个时移时钟信号中的相应一个控制。 多个时移时钟信号可以例如由至少一个延迟元件产生。 多个并行数据路径可以是基本相同的，并且包括例如至少一个锁存器或至少一个触发器。 补偿可以任选地用于例如过程拐角，电源电压，老化和工作温度的变化。

公开(公告)号：US20060197609A1

公开(公告)日：2006-09-07

申请号：US11071707

申请日：2005-03-03

申请人： Christopher Abel

发明人： Christopher Abel

IPC分类号： H03L7/00

CPC分类号： H03L7/0995 ,  H03L7/093

摘要： Embodiments of the invention include a voltage-controlled oscillator (VCO) circuit in which the gain of the VCO is proportional to the output or operating frequency of the VCO. The VCO circuit includes a voltage-controlled oscillator, a current scaling block, and a summing node. The summing node couples a VCO control current and a VCO reference current into the current scaling block. The current scaling block scales the sum of the currents by a scaling factor. The output of the current scaling block, which is coupled to the input of the VCO, provides a bias current to the VCO, which bias current adjusts the oscillation frequency of the oscillator. The VCO control current and the VCO reference current are scaled by the same scaling factor, thus allowing the gain of the VCO to be proportional to but not dependent on the output frequency of the VCO.

摘要翻译： 本发明的实施例包括压控振荡器（VCO）电路，其中VCO的增益与VCO的输出或工作频率成比例。 VCO电路包括压控振荡器，电流缩放块和求和节点。 求和节点将VCO控制电流和VCO参考电流耦合到当前缩放块中。 当前缩放块按比例因子缩放电流之和。 耦合到VCO的输入的电流缩放块的输出向VCO提供偏置电流，该偏置电流调节振荡器的振荡频率。 VCO控制电流和VCO参考电流按照相同的缩放因子进行缩放，从而允许VCO的增益与VCO的输出频率成正比，但不取决于VCO的输出频率。

公开(公告)号：US08385493B2

公开(公告)日：2013-02-26

申请号：US12755522

申请日：2010-04-07

申请人： Christopher Abel ,  Joseph Anidjar ,  Vladimir Sindalovsky ,  Craig Ziemer

发明人： Christopher Abel ,  Joseph Anidjar ,  Vladimir Sindalovsky ,  Craig Ziemer

IPC分类号： H04L7/02

CPC分类号： H04L7/0008

摘要： Disclosed is a system and method for improving the linearity of a clock and data recovery (CDR) circuit. In one embodiment, a data stream is received, and the phase of a clock signal is adjusted using two interpolators. The phase of the output signal of the second interpolator is adjusted simultaneously with, and complementary to, adjusting the phase of the first interpolator. The first interpolator's output signal is injected into a first delay cell in a delay loop having a plurality of delay cells, and the output of the second interpolator is inactivated. When the maximum phase of the first interpolator's output signal is reached, the second interpolator's output signal is injected into another one of the delay cells, and the first interpolator's output signal is inactivated. The data stream is then recovered using the output of the delay loop as a clock signal.

摘要翻译： 公开了一种用于提高时钟和数据恢复（CDR）电路的线性度的系统和方法。 在一个实施例中，接收数据流，并且使用两个内插器调整时钟信号的相位。 第二内插器的输出信号的相位与调整第一内插器的相位同时调整并补充。 第一内插器的输出信号被注入到具有多个延迟单元的延迟环中的第一延迟单元中，并且第二内插器的输出被非激活。 当达到第一内插器的输出信号的最大相位时，第二内插器的输出信号被注入另一个延迟单元，并且第一内插器的输出信号被去激活。 然后使用延迟环路的输出作为时钟信号来恢复数据流。

公开(公告)号：US20100219996A1

公开(公告)日：2010-09-02

申请号：US12380639

申请日：2009-03-02

申请人： Christopher Abel ,  Mohammad Mobin ,  Robert Kapuschinsky ,  Lane Smith ,  Paul Tracy ,  Gregory Sheets

发明人： Christopher Abel ,  Mohammad Mobin ,  Robert Kapuschinsky ,  Lane Smith ,  Paul Tracy ,  Gregory Sheets

IPC分类号： H03M1/10

CPC分类号： H04L25/061

摘要： In described embodiments, a communication system employing, for example, clock and data recovery (CDR) detects and applies correction for DC offset in an input data stream signal, termed as “DC offset calibration”. DC offset calibration applies static calibration for DC offset in input circuits, such as an input amplifier and detection latches, without input data, and applies statistical calibration for DC offset during operation with an input data stream to correct for dynamic shifts in DC level. Such DC offset calibration employs data eye measurements of the input data stream for detection of DC offset, and applies an opposite DC offset to maintain a relatively balanced data eye during live traffic.

摘要翻译： 在所描述的实施例中，采用例如时钟和数据恢复（CDR）的通信系统在输入数据流信号中检测并应用校正DC偏移，称为“DC偏移校准”。 DC偏移校准在输入电路（如输入放大器和检测锁存器）中对直流偏移进行静态校准，无输入数据，并在输入数据流运行期间对DC偏移进行统计校准，以校正直流电平的动态偏移。 这种DC偏移校准使用用于检测DC偏移的输入数据流的数据眼睛测量，并施加相反的DC偏移以在实时业务期间维持相对平衡的数据眼睛。

公开(公告)号：US20100195777A1

公开(公告)日：2010-08-05

申请号：US12755522

申请日：2010-04-07

申请人： Christopher Abel ,  Joseph Anidjar ,  Vladimir Sindalovsky ,  Craig Ziemer

发明人： Christopher Abel ,  Joseph Anidjar ,  Vladimir Sindalovsky ,  Craig Ziemer

IPC分类号： H04L7/033

CPC分类号： H04L7/0008

摘要： Disclosed is a system and method for improving the linearity of a clock and data recovery (CDR) circuit. In one embodiment, a data stream is received, and the phase of a clock signal is adjusted using two interpolators. The phase of the output signal of the second interpolator is adjusted simultaneously with, and complementary to, adjusting the phase of the first interpolator. The first interpolator's output signal is injected into a first delay cell in a delay loop having a plurality of delay cells, and the output of the second interpolator is inactivated. When the maximum phase of the first interpolator's output signal is reached, the second interpolator's output signal is injected into another one of the delay cells, and the first interpolator's output signal is inactivated. The data stream is then recovered using the output of the delay loop as a clock signal.

摘要翻译： 公开了一种用于提高时钟和数据恢复（CDR）电路的线性度的系统和方法。 在一个实施例中，接收数据流，并且使用两个内插器调整时钟信号的相位。 第二内插器的输出信号的相位与调整第一内插器的相位同时调整并补充。 第一内插器的输出信号被注入到具有多个延迟单元的延迟环中的第一延迟单元中，并且第二内插器的输出被去激活。 当达到第一内插器的输出信号的最大相位时，第二内插器的输出信号被注入另一个延迟单元，并且第一内插器的输出信号被去激活。 然后使用延迟环路的输出作为时钟信号来恢复数据流。

公开(公告)号：US07724857B2

公开(公告)日：2010-05-25

申请号：US11375828

申请日：2006-03-15

申请人： Christopher Abel ,  Joseph Anidjar ,  Vladimir Sindalovsky ,  Craig Ziemer

发明人： Christopher Abel ,  Joseph Anidjar ,  Vladimir Sindalovsky ,  Craig Ziemer

IPC分类号： H04L7/00

CPC分类号： H04L7/0008

摘要： Disclosed is a system and method for improving the linearity of a clock and data recovery (CDR) circuit. In one embodiment, a data stream is received, and the phase of a clock signal is adjusted using two interpolators. The phase of the output signal of the second interpolator is adjusted simultaneously with, and complementary to, adjusting the phase of the first interpolator. The first interpolator's output signal is injected into a first delay cell in a delay loop having a plurality of delay cells, and the output of the second interpolator is inactivated. When the maximum phase of the first interpolator's output signal is reached, the second interpolator's output signal is injected into another one of the delay cells, and the first interpolator's output signal is inactivated. The data stream is then recovered using the output of the delay loop as a clock signal.

摘要翻译： 公开了一种用于提高时钟和数据恢复（CDR）电路的线性度的系统和方法。 在一个实施例中，接收数据流，并且使用两个内插器调整时钟信号的相位。 第二内插器的输出信号的相位与调整第一内插器的相位同时调整并补充。 第一内插器的输出信号被注入到具有多个延迟单元的延迟环中的第一延迟单元中，并且第二内插器的输出被非激活。 当达到第一内插器的输出信号的最大相位时，第二内插器的输出信号被注入另一个延迟单元，并且第一内插器的输出信号被去激活。 然后使用延迟环路的输出作为时钟信号来恢复数据流。

公开(公告)号：US20060284687A1

公开(公告)日：2006-12-21

申请号：US11154314

申请日：2005-06-16

申请人： Christopher Abel

发明人： Christopher Abel

IPC分类号： H03L7/00

CPC分类号： H03L7/093 ,  H03L7/107

摘要： An integrated circuit includes a phase-locked loop (PLL) in which the loop bandwidth of the PLL is proportional to the input frequency of the PLL. The PLL includes a phase/frequency detector (PFD), a charge pump, a loop filter, and a voltage-controlled oscillator (VCO) that generates the PLL output clock. The VCO includes a current scaling block that scales the sum of a variable current, which is proportional to the loop filter voltage, and a fixed current. The frequency of the PLL output clock is a function of the current output from the current scaling block. Since the same scaling factor is applied to both the fixed current and the variable current, the gain from the loop filter voltage to the PLL output frequency is proportional to the PLL output frequency, and thus the loop bandwidth of the PLL is proportional to the PLL input frequency.

摘要翻译： 集成电路包括锁相环（PLL），其中PLL的环路带宽与PLL的输入频率成比例。 PLL包括产生PLL输出时钟的相位/频率检测器（PFD），电荷泵，环路滤波器和压控振荡器（VCO）。 VCO包括电流缩放块，其缩放与环路滤波器电压成比例的可变电流和固定电流的和。 PLL输出时钟的频率是当前缩放块的电流输出的函数。 由于固定电流和可变电流都应用相同的比例因子，所以从环路滤波器电压到PLL输出频率的增益与PLL输出频率成比例，因此PLL的环路带宽与PLL成正比 输入频率。