公开(公告)号：US20220113751A1

公开(公告)日：2022-04-14

申请号：US17645896

申请日：2021-12-23

Applicant: James Keith Hodgson ,  Fabrice Paillet ,  Christopher J. Mandic ,  Cary Renzema ,  Anand Ramasundar ,  Sami Hyvonen ,  Po-Cheng Chen ,  Alex Santiago Rodriguez ,  Sergio Carlo Rodriguez ,  Saravanan Ramamoorthy ,  Ruthvin Jeevan Suvarna

Inventor： James Keith Hodgson ,  Fabrice Paillet ,  Christopher J. Mandic ,  Cary Renzema ,  Anand Ramasundar ,  Sami Hyvonen ,  Po-Cheng Chen ,  Alex Santiago Rodriguez ,  Sergio Carlo Rodriguez ,  Saravanan Ramamoorthy ,  Ruthvin Jeevan Suvarna

IPC: G05F1/46

Abstract: A reduced-size replica of power gate transistors may be used within a closed-loop voltage regulator to measure the average current delivered by the transistors in the non-replica power gate. The measured current is compared against a known reference current, and a feedback loop is used to modify the gate bias of the power gate and replica power gate transistors. An improved current sensing power gate replica solution may include measuring current from a small replica of the power gate and extrapolating the total current by digitally multiplying the replica current by the ratio of the size of the enabled power gates to the size of the replicas. The current through the replicas, which substantially matches the current in equivalent power gate devices, may be collected on an analog bus and conducted across a known resistor to generate a voltage that determines an estimated current of the power gate devices.

公开(公告)号：US20230208432A1

公开(公告)日：2023-06-29

申请号：US17561136

申请日：2021-12-23

Applicant: Fabrice Paillet ,  Jason Muhlestein ,  James Keith Hodgson ,  SHIVADARSHAN BIDADI RAJEURS ,  George Matthew ,  Anand Ramasundar ,  Cary Renzema ,  Po-Cheng Chen ,  Sergio Carlo Rodriguez ,  Seng Rou Tey

Inventor： Fabrice Paillet ,  Jason Muhlestein ,  James Keith Hodgson ,  SHIVADARSHAN BIDADI RAJEURS ,  George Matthew ,  Anand Ramasundar ,  Cary Renzema ,  Po-Cheng Chen ,  Sergio Carlo Rodriguez ,  Seng Rou Tey

IPC: H03M1/78 ,  H02M3/157 ,  H02M1/00

CPC classification number: H03M1/785 ,  H02M3/157 ,  H02M1/0025

Abstract: An apparatus, system, and method for digital-to-analog (converter) control are provided. A DAC includes a first resistor ladder including a plurality of first electrical taps into different portions of the first resistor ladder, first and second pass gate trees coupled to receive outputs from the first electrical taps, first and second buffers coupled to receive outputs from the first and second pass gate trees, respectively, a second resistor ladder coupled to receive and be biased by outputs of the first and second buffers, the second resistor ladder including a plurality of second electrical taps into different portions of the second resistor ladder, and third, fourth, and fifth pass gate trees coupled to receive outputs from the second electrical taps.

公开(公告)号：US20230092022A1

公开(公告)日：2023-03-23

申请号：US17483381

申请日：2021-09-23

Applicant: Fabrice Paillet ,  Anand Ramasundar ,  Khondker Ahmed ,  Harish K. Krishnamurthy ,  Cary Renzema ,  Christopher Mandic ,  James Keith Hodgson

Inventor： Fabrice Paillet ,  Anand Ramasundar ,  Khondker Ahmed ,  Harish K. Krishnamurthy ,  Cary Renzema ,  Christopher Mandic ,  James Keith Hodgson

IPC: G05F1/56

Abstract: An apparatus, system, and method for voltage regulator (VR) control are provided. An apparatus can include first, second, and third comparators configured to determine whether a load voltage (VLOAD) drops below a lower non-linear control (NLC) threshold, drops below a lower linear control (LC) threshold, and exceeds an upper LC threshold, respectively. The apparatus can include power gates (PGs) configured to adjust an output voltage (VOUT) based on a provided power gate (PG) code. The apparatus can include voltage regulator (VR) controller circuitry comprising synchronous LC circuitry and asynchronous NLC circuitry, the LC circuitry configured to increment or decrement the PG code responsive to the VLOAD dropping below the LC threshold and exceeding the upper LC threshold, respectively, and the NLC circuitry configured to increase the PG code based on a number of consecutive NLC droop events and responsive to the VLOAD dropping below the lower NLC threshold.