公开(公告)号：US20230208432A1

公开(公告)日：2023-06-29

申请号：US17561136

申请日：2021-12-23

申请人： Fabrice Paillet ,  Jason Muhlestein ,  James Keith Hodgson ,  SHIVADARSHAN BIDADI RAJEURS ,  George Matthew ,  Anand Ramasundar ,  Cary Renzema ,  Po-Cheng Chen ,  Sergio Carlo Rodriguez ,  Seng Rou Tey

发明人： Fabrice Paillet ,  Jason Muhlestein ,  James Keith Hodgson ,  SHIVADARSHAN BIDADI RAJEURS ,  George Matthew ,  Anand Ramasundar ,  Cary Renzema ,  Po-Cheng Chen ,  Sergio Carlo Rodriguez ,  Seng Rou Tey

IPC分类号： H03M1/78 ,  H02M3/157 ,  H02M1/00

CPC分类号： H03M1/785 ,  H02M3/157 ,  H02M1/0025

摘要： An apparatus, system, and method for digital-to-analog (converter) control are provided. A DAC includes a first resistor ladder including a plurality of first electrical taps into different portions of the first resistor ladder, first and second pass gate trees coupled to receive outputs from the first electrical taps, first and second buffers coupled to receive outputs from the first and second pass gate trees, respectively, a second resistor ladder coupled to receive and be biased by outputs of the first and second buffers, the second resistor ladder including a plurality of second electrical taps into different portions of the second resistor ladder, and third, fourth, and fifth pass gate trees coupled to receive outputs from the second electrical taps.

公开(公告)号：US10348200B2

公开(公告)日：2019-07-09

申请号：US14294045

申请日：2014-06-02

申请人： Tarun Mahajan ,  Ramnarayanan Ram Muthukaruppan ,  Srinivasulu Malepati ,  George Matthew

发明人： Tarun Mahajan ,  Ramnarayanan Ram Muthukaruppan ,  Srinivasulu Malepati ,  George Matthew

IPC分类号： H02M1/00 ,  H02M1/32 ,  H02M1/40 ,  G01R19/25 ,  H02M1/088 ,  H02M3/157 ,  H02M3/158

摘要： Described is an apparatus which comprises: an output node; a capacitor; an inductor having a first terminal coupled to the output node, and a second terminal coupled to the capacitor; a bridge to receive an input power supply and to generate a switching voltage signal at the output node; and a current sensor to determine slope of the switching voltage signal on the output node.

公开(公告)号：US08180811B2

公开(公告)日：2012-05-15

申请号：US12907632

申请日：2010-10-19

申请人： Nagaraj Shyam ,  Craig Keatley Harmer ,  George Matthew

发明人： Nagaraj Shyam ,  Craig Keatley Harmer ,  George Matthew

IPC分类号： G06F17/30

CPC分类号： G06F17/30094

摘要： A list of data structures (e.g., inodes) can be accessed, and the data structures in the list can be examined. If a data structure is examined, a counter value associated with the data structure is changed to a generation number that is associated with the examination. Subsequently, the counter values can be used to identify unreferenced data structures. More specifically, the counter value for an unreferenced data structure will be different from the generation number for the most recently performed examination.

摘要翻译： 可以访问数据结构（例如，inode）的列表，并且可以检查列表中的数据结构。 如果检查数据结构，则将与数据结构相关联的计数器值更改为与检查相关联的代数。 随后，可以使用计数器值来识别未引用的数据结构。 更具体地，未参考数据结构的计数器值将与最近执行的检查的代数不同。