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    Circuit structures and methods with BEOL layers configured to block electromagnetic edge interference
    2.
    发明授权
    Circuit structures and methods with BEOL layers configured to block electromagnetic edge interference 有权
    BEOL层的电路结构和方法被配置为阻止电磁边缘干扰

    公开(公告)号：US08138563B2

    公开(公告)日：2012-03-20

    申请号：US12188243

    申请日：2008-08-08

    申请人： Choongyeun Cho ,  Daeik Kim ,  Jonghae Kim ,  Moon Ju Kim ,  James R. Moulic

    发明人： Choongyeun Cho ,  Daeik Kim ,  Jonghae Kim ,  Moon Ju Kim ,  James R. Moulic

    IPC分类号： H01L29/82

    CPC分类号： H01L23/5225 ,  H01L23/552 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Back-end-of-line (BEOL) circuit structures and methods are provided for blocking externally-originating or internally-originating electromagnetic edge interference. One such BEOL circuit structure includes a semiconductor substrate supporting one or more integrated circuits, and multiple BEOL layers disposed over the semiconductor substrate. The multiple BEOL layers extend to an edge of the circuit structure and include at least one vertically-extending conductive pattern disposed adjacent to the edge of the circuit structure. The vertically-extending conductive pattern is defined, at least partially, by a plurality of elements disposed in the multiple BEOL layers. The plurality of elements are uniformly arrayed at the edge of the circuit structure in a first direction or a second direction throughout at least a portion thereof. The plurality of elements are sized and positioned in the first direction or the second direction to block electromagnetic interference of a particular wavelength from passing therethrough.

    摘要翻译： 提供了后端行（BEOL）电路结构和方法来阻止外部来源或内部产生的电磁边缘干扰。 一个这样的BEOL电路结构包括支撑一个或多个集成电路的半导体衬底和设置在半导体衬底上的多个BEOL层。 多个BEOL层延伸到电路结构的边缘并且包括邻近电路结构的边缘布置的至少一个垂直延伸的导电图案。 至少部分地由设置在多个BEOL层中的多个元件限定垂直延伸的导电图案。 多个元件在电路结构的边缘沿其第一方向或第二方向均匀地排列在其至少一部分上。 多个元件的大小和尺寸设置在第一方向或第二方向上，以阻止特定波长的电磁干扰通过。

    MEMORY TO MEMORY COMMUNICATION AND STORAGE FOR HYBRID SYSTEMS
    4.
    发明申请
    MEMORY TO MEMORY COMMUNICATION AND STORAGE FOR HYBRID SYSTEMS 有权
    对混合系统的记忆体通信和存储的记忆

    公开(公告)号：US20090150555A1

    公开(公告)日：2009-06-11

    申请号：US11951709

    申请日：2007-12-06

    申请人： Moon J. Kim ,  Rajaram B. krishnamurthy ,  James R. Moulic

    发明人： Moon J. Kim ,  Rajaram B. krishnamurthy ,  James R. Moulic

    IPC分类号： G06F15/16

    CPC分类号： H04L67/1097 ,  G06F3/0605 ,  G06F3/0638 ,  G06F3/064 ,  G06F3/067

    摘要： The present invention relates to memory to memory communication and storage for hybrid systems. Under the present invention, a data stream is received on a first computing device of a hybrid system. An attempt is made to store the data stream on the first computing device up to a per stream limit and a total storage limit of the first computing device. It is then determined whether to store at least a portion of the data stream on a second computing device of the hybrid system that is in communication with the first computing device. This decision is based on the per stream limit and the total storage limit of the first computing device as well as a per stream limit and a total storage limit of the second computing device. Thereafter, the at least a portion of the data stream and a control signal are communicated to the second computing device for storage.

    摘要翻译： 本发明涉及用于混合系统的存储器到存储器通信和存储。 在本发明中，在混合系统的第一计算设备上接收数据流。 尝试将数据流存储在第一计算设备上，直到第一计算设备的每流限制和总存储限制。 然后确定是否将数据流的至少一部分存储在与第一计算设备通信的混合系统的第二计算设备上。 该决定基于第一计算设备的每流限制和总存储限制以及第二计算设备的每流限制和总存储限制。 此后，数据流的至少一部分和控制信号被传送到第二计算设备以进行存储。

    UNIVERSAL IMAGE PROCESSING
    5.
    发明申请
    UNIVERSAL IMAGE PROCESSING 有权
    通用图像处理

    公开(公告)号：US20080181471A1

    公开(公告)日：2008-07-31

    申请号：US11668875

    申请日：2007-01-30

    申请人： William Hyun-Kee Chung ,  Bruce A. Foster ,  Moon J. Kim ,  James R. Moulic

    发明人： William Hyun-Kee Chung ,  Bruce A. Foster ,  Moon J. Kim ,  James R. Moulic

    IPC分类号： G06K9/00

    CPC分类号： G06T1/00 ,  A61B6/463 ,  A61B6/464 ,  A61B6/5247 ,  A61B6/563 ,  G06F19/00 ,  G06F19/321 ,  G06T7/00 ,  G06T11/003

    摘要： The present invention provides a universal and centralized image (e.g., medical, bio-molecular, etc.) processing system platform. The invention permits sharing both computation and visualization across a single universal platform, thus allowing for sharing of computing resources and visualization of images on a variety of imaging (client) devices without high-performance graphical display cards. In a typical embodiment a (e.g., medical) image 2D linear registration algorithm is implemented on a Cell Broadband Engine processor, which has nine processor cores on a chip and has a 4-way SIMD unit for each core.

    摘要翻译： 本发明提供了一种通用且集中的图像（例如医疗，生物分子等）处理系统平台。 本发明允许在单个通用平台上共享计算和可视化，从而允许在不具有高性能图形显示卡的各种成像（客户端）设备上共享计算资源和可视化图像。 在典型的实施例中，在Cell Broadband Engine处理器上实现（例如，医学）图像2D线性注册算法，该处理器在芯片上具有九个处理器核心，并且具有用于每个核心的4路SIMD单元。

    Generating and evaluating expert networks
    7.
    发明授权
    Generating and evaluating expert networks 有权
    生成和评估专家网络

    公开(公告)号：US08996341B2

    公开(公告)日：2015-03-31

    申请号：US13610116

    申请日：2012-09-11

    申请人： Winnie W. Cheng ,  Gengxin Miao ,  James R. Moulic ,  Shu Tao

    发明人： Winnie W. Cheng ,  Gengxin Miao ,  James R. Moulic ,  Shu Tao

    IPC分类号： G06G7/48 ,  H04L12/24

    CPC分类号： H04L41/142 ,  H04L41/0816 ,  H04L41/145 ,  H04L41/22 ,  Y04S40/162

    摘要： A system comprises a modeling component, a routing component, a simulator component and a configuration component. The modeling component is operative to obtain at least one model of at least one collaborative network. The routing component is operative to model at least one routing pattern for one or more nodes of a given collaborative network. The simulator component is operative to simulate one or more virtual network topologies of the given collaborative network using the at least one model and the at least one routing pattern. The configuration component is operative to configure one or more given virtual network topologies on the given collaborative network. The collaborative network comprises a plurality of nodes and one or more edges between pairs of the plurality of nodes. The modeling component, routing component, simulator component and configuration component are executed by at least one processing device.

    摘要翻译： 系统包括建模组件，路由组件，模拟器组件和配置组件。 建模组件可操作以获得至少一个协作网络的至少一个模型。 路由组件可操作以对给定协作网络中的一个或多个节点建立至少一个路由模式。 所述模拟器组件可操作以使用所述至少一个模型和所述至少一个路由模式来模拟给定协作网络的一个或多个虚拟网络拓扑。 配置组件可用于在给定协作网络上配置一个或多个给定的虚拟网络拓扑。 协作网络包括多个节点和多个节点对之间的一个或多个边缘。 建模组件，路由组件，模拟器组件和配置组件由至少一个处理设备执行。

    Heterogeneous image processing system
    8.
    发明授权
    Heterogeneous image processing system 有权
    异构图像处理系统

    公开(公告)号：US08331737B2

    公开(公告)日：2012-12-11

    申请号：US11738711

    申请日：2007-04-23

    申请人： William H. Chung ,  Moon J. Kim ,  James R. Moulic ,  Toshiyuki Sanuki

    发明人： William H. Chung ,  Moon J. Kim ,  James R. Moulic ,  Toshiyuki Sanuki

    IPC分类号： G06K9/60

    CPC分类号： G06T1/20

    摘要： The present invention relates to machine vision computing environments, and more specifically relates to a system and method for selectively accelerating the execution of image processing applications using a multi-core processor system. To this extent, a multi-core processor system is generally defined as one that is multi-platform, and potentially distributed via a network or other connection. The invention provides a machine vision system and method for executing image processing applications referred to herein as an image co-processor that comprises (among other things) a plurality of multi-core processors (MCPs) that work to process multiple images in an accelerated fashion.

    摘要翻译： 本发明涉及机器视觉计算环境，更具体地涉及一种用于使用多核处理器系统选择性地加速图像处理应用的执行的系统和方法。 在这种情况下，多核处理器系统通常被定义为多平台的，并且可能通过网络或其他连接分布。 本发明提供了一种用于执行图像处理应用的机器视觉系统和方法，这里称为图像协处理器，其包括（尤其是）多个多核处理器（MCP），其工作以加速方式处理多个图像 。

    Heterogeneous image processing system
    9.
    发明授权
    Heterogeneous image processing system 有权
    异构图像处理系统

    公开(公告)号：US08326092B2

    公开(公告)日：2012-12-04

    申请号：US11738723

    申请日：2007-04-23

    申请人： William H. Chung ,  Moon J. Kim ,  James R. Moulic ,  Toshiyuki Sanuki

    发明人： William H. Chung ,  Moon J. Kim ,  James R. Moulic ,  Toshiyuki Sanuki

    IPC分类号： G06K9/60

    CPC分类号： G06T1/20

    摘要： The present invention relates to machine vision computing environments, and more specifically relates to a system and method for selectively accelerating the execution of image processing applications using a hybrid computing system. To this extent, a hybrid system is generally defined as one that is multi-platform, and potentially distributed via a network or other connection. The invention provides a machine vision system and method for executing image processing applications on a hybrid image processing system referred to herein as an image co-processor that comprises (among other things) a plurality of special purpose engines (SPEs) that work to process multiple images in an accelerated fashion.

    摘要翻译： 本发明涉及机器视觉计算环境，更具体地涉及一种用于使用混合计算系统选择性地加速图像处理应用的执行的系统和方法。 在这种程度上，混合系统通常被定义为多平台的，并且可能通过网络或其他连接分发。 本发明提供了一种用于在这里称为图像协处理器的混合图像处理系统上执行图像处理应用的机器视觉系统和方法，该图像协处理器包括（尤其是）多个专用引擎（SPE），其用于处理多个 图像以加速的方式。

    Circuit structures and methods with BEOL layers configured to block electromagnetic edge interference
    10.
    发明授权
    Circuit structures and methods with BEOL layers configured to block electromagnetic edge interference 有权

    公开(公告)号：US08273648B2

    公开(公告)日：2012-09-25

    申请号：US13369592

    申请日：2012-02-09

    申请人： Choongyeun Cho ,  Daeik Kim ,  Jonghae Kim ,  Moon Ju Kim ,  James R. Moulic

    发明人： Choongyeun Cho ,  Daeik Kim ,  Jonghae Kim ,  Moon Ju Kim ,  James R. Moulic

    IPC分类号： H01L21/3205

    CPC分类号： H01L23/5225 ,  H01L23/552 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Back-end-of-line (BEOL) circuit structures and methods are provided for blocking externally-originating or internally-originating electromagnetic edge interference. One such BEOL circuit structure includes a semiconductor substrate supporting one or more integrated circuits, and multiple BEOL layers disposed over the semiconductor substrate. The multiple BEOL layers extend to an edge of the circuit structure and include at least one vertically-extending conductive pattern disposed adjacent to the edge of the circuit structure. The vertically-extending conductive pattern is defined, at least partially, by a plurality of elements disposed in the multiple BEOL layers. The plurality of elements are uniformly arrayed at the edge of the circuit structure in a first direction or a second direction throughout at least a portion thereof. The plurality of elements are sized and positioned in the first direction or the second direction to block electromagnetic interference of a particular wavelength from passing therethrough.