公开(公告)号：US07687338B2

公开(公告)日：2010-03-30

申请号：US11950572

申请日：2007-12-05

申请人： Sameer Jain ,  Shreesh Narasimha ,  Karen A. Nummy ,  Viorel Ontalus ,  Jang H. Sim

发明人： Sameer Jain ,  Shreesh Narasimha ,  Karen A. Nummy ,  Viorel Ontalus ,  Jang H. Sim

IPC分类号： H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848 ,  Y10S257/90

摘要： Embodiments of the invention provide a method of forming embedded silicon germanium (eSiGe) in source and drain regions of a p-type field-effect-transistor (pFET) through a disposable spacer process; depositing a gap-filling layer directly on the eSiGe in the source and drain regions in a first process; depositing a layer of offset spacer material on top of the gap-filling layer in a second process different from the first process; etching the offset spacer material and the gap-filling layer, thus forming a set of offset spacers and exposing the eSiGe in the source and drain regions of the pFET; and finishing formation of the pFET.

摘要翻译： 本发明的实施例提供了通过一次性间隔物工艺在p型场效应晶体管（pFET）的源区和漏区中形成嵌入硅锗（eSiGe）的方法; 在第一过程中在源极和漏极区域中的eSiGe上直接沉积间隙填充层; 在与第一工艺不同的第二工艺中，在间隙填充层的顶部上沉积一层偏移间隔物材料; 蚀刻偏移间隔物材料和间隙填充层，从而形成一组偏移间隔物并暴露p​​FET的源区和漏区中的eSiGe; 并完成pFET的形成。

公开(公告)号：US20090148988A1

公开(公告)日：2009-06-11

申请号：US11950572

申请日：2007-12-05

申请人： Sameer Jain ,  Shreesh Narasimha ,  Karen A. Nummy ,  Viorel Ontalus ,  Jang H. Sim

发明人： Sameer Jain ,  Shreesh Narasimha ,  Karen A. Nummy ,  Viorel Ontalus ,  Jang H. Sim

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848 ,  Y10S257/90

摘要： Embodiments of the invention provide a method of forming embedded silicon germanium (eSiGe) in source and drain regions of a p-type field-effect-transistor (pFET) through a disposable spacer process; depositing a gap-filling layer directly on the eSiGe in the source and drain regions in a first process; depositing a layer of offset spacer material on top of the gap-filling layer in a second process different from the first process; etching the offset spacer material and the gap-filling layer, thus forming a set of offset spacers and exposing the eSiGe in the source and drain regions of the pFET; and finishing formation of the pFET.

摘要翻译： 本发明的实施例提供了通过一次性间隔物工艺在p型场效应晶体管（pFET）的源区和漏区中形成嵌入硅锗（eSiGe）的方法; 在第一过程中在源极和漏极区域中的eSiGe上直接沉积间隙填充层; 在与第一工艺不同的第二工艺中，在间隙填充层的顶部上沉积一层偏移间隔物材料; 蚀刻偏移间隔物材料和间隙填充层，从而形成一组偏移间隔物并暴露p​​FET的源区和漏区中的eSiGe; 并完成pFET的形成。

公开(公告)号：US20090146223A1

公开(公告)日：2009-06-11

申请号：US11950574

申请日：2007-12-05

申请人： Sameer H. Jain ,  Shreesh Narasimha ,  Karen A. Nummy ,  Katsunori Onishi ,  Viorel C. Ontalus ,  Jang H. Sim

发明人： Sameer H. Jain ,  Shreesh Narasimha ,  Karen A. Nummy ,  Katsunori Onishi ,  Viorel C. Ontalus ,  Jang H. Sim

IPC分类号： H01L29/94 ,  H01L21/8236

CPC分类号： H01L21/26506 ,  H01L21/26513 ,  H01L21/268 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/808 ,  H01L29/812

摘要： A method removes the spacers from the sides of a transistor gate stack, and after the spacers are removed, the method implants an additional impurity into surface regions of the substrate not protected by the gate conductor (or alternatively just amorphizes these surface regions, without adding more impurity). The method then performs a laser anneal on the additional impurity (to activate the additional impurity) or amorphized regions (to recrystallize the amorphized regions). After this, permanent spacers are formed on the sidewalls of the gate conductor. Then, the surface regions of the substrate not protected by the gate conductor and the permanent spacers are silicided, to create silicide source/drain regions. This forms the silicide regions in the additional impurity or in the recrystallized amorphized regions to reduce the source/drain resistance by improving the active dopant concentration at the silicon-silicide interface.

摘要翻译： 一种方法从晶体管栅极堆叠的侧面去除间隔物，并且在间隔物被去除之后，该方法将不附加栅极导体保护的衬底的另外的杂质注入到衬底的表面区域中（或者只是将这些表面区域非晶化，而不添加 更多的杂质）。 然后，该方法对另外的杂质（以激活附加杂质）或非晶化区域（使非晶化区域重结晶）进行激光退火。 之后，在栅极导体的侧壁上形成永久的间隔物。 然后，将不被栅极导体和永久性间隔物保护的衬底的表面区域硅化，以产生硅化物源极/漏极区域。 这会在附加杂质或再结晶非晶化区域中形成硅化物区域，以通过改善硅硅化物界面处的活性掺杂剂浓度来降低源/漏电阻。