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    PROCESS AND METHOD TO LOWER CONTACT RESISTANCE
    1.
    发明申请
    PROCESS AND METHOD TO LOWER CONTACT RESISTANCE 审中-公开
    降低接触电阻的方法和方法

    公开(公告)号：US20090146223A1

    公开(公告)日：2009-06-11

    申请号：US11950574

    申请日：2007-12-05

    申请人： Sameer H. Jain ,  Shreesh Narasimha ,  Karen A. Nummy ,  Katsunori Onishi ,  Viorel C. Ontalus ,  Jang H. Sim

    发明人： Sameer H. Jain ,  Shreesh Narasimha ,  Karen A. Nummy ,  Katsunori Onishi ,  Viorel C. Ontalus ,  Jang H. Sim

    IPC分类号： H01L29/94 ,  H01L21/8236

    CPC分类号： H01L21/26506 ,  H01L21/26513 ,  H01L21/268 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/808 ,  H01L29/812

    摘要： A method removes the spacers from the sides of a transistor gate stack, and after the spacers are removed, the method implants an additional impurity into surface regions of the substrate not protected by the gate conductor (or alternatively just amorphizes these surface regions, without adding more impurity). The method then performs a laser anneal on the additional impurity (to activate the additional impurity) or amorphized regions (to recrystallize the amorphized regions). After this, permanent spacers are formed on the sidewalls of the gate conductor. Then, the surface regions of the substrate not protected by the gate conductor and the permanent spacers are silicided, to create silicide source/drain regions. This forms the silicide regions in the additional impurity or in the recrystallized amorphized regions to reduce the source/drain resistance by improving the active dopant concentration at the silicon-silicide interface.

    摘要翻译： 一种方法从晶体管栅极堆叠的侧面去除间隔物，并且在间隔物被去除之后，该方法将不附加栅极导体保护的衬底的另外的杂质注入到衬底的表面区域中（或者只是将这些表面区域非晶化，而不添加 更多的杂质）。 然后，该方法对另外的杂质（以激活附加杂质）或非晶化区域（使非晶化区域重结晶）进行激光退火。 之后，在栅极导体的侧壁上形成永久的间隔物。 然后，将不被栅极导体和永久性间隔物保护的衬底的表面区域硅化，以产生硅化物源极/漏极区域。 这会在附加杂质或再结晶非晶化区域中形成硅化物区域，以通过改善硅硅化物界面处的活性掺杂剂浓度来降低源/漏电阻。

    REDUCING DISLOCATION FORMATION IN SEMICONDUCTOR DEVICES THROUGH TARGETED CARBON IMPLANTATION
    2.
    发明申请
    REDUCING DISLOCATION FORMATION IN SEMICONDUCTOR DEVICES THROUGH TARGETED CARBON IMPLANTATION 失效
    通过目标碳植入减少半导体器件中的分离形成

    公开(公告)号：US20120184075A1

    公开(公告)日：2012-07-19

    申请号：US13009020

    申请日：2011-01-19

    申请人： Anthony G. Domenicucci ,  Shreesh Narasimha ,  Karen A. Nummy ,  Viorel C. Ontalus ,  Yun-Yu Wang

    发明人： Anthony G. Domenicucci ,  Shreesh Narasimha ,  Karen A. Nummy ,  Viorel C. Ontalus ,  Yun-Yu Wang

    IPC分类号： H01L21/336 ,  H01L21/84

    CPC分类号： H01L29/7847 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/6659 ,  H01L29/7833

    摘要： A method of forming a semiconductor device includes implanting an amorphizing species into a crystalline semiconductor substrate, the substrate having a transistor gate structure formed thereupon. Carbon is implanted into amorphized regions of the substrate, with specific implant conditions tailored such that the peak concentration of carbon species coincides with the end of the stacking faults, where the stacking faults are created during the recrystallization anneal. The implanted carbon pins partial dislocations so as to prevent the dislocations from disassociating from the end of the stacking faults and moving to a region in the substrate directly below the transistor gate structure. This removes the defects, which cause device leakage fail.

    摘要翻译： 形成半导体器件的方法包括将非晶化物质注入晶体半导体衬底中，所述衬底具有在其上形成的晶体管栅极结构。 碳被植入到基底的非晶化区域中，其特定的植入条件被定制，使得碳类的峰值浓度与堆垛层错的结束一致，其中在重结晶退火期间产生堆垛层错。 植入的碳引脚部分位错，以防止位错从堆垛层错的末端脱离，并移动到晶体管栅极结构正下方的衬底区域。 这消除了导致设备泄漏失败的缺陷。

    Reducing dislocation formation in semiconductor devices through targeted carbon implantation
    3.
    发明授权
    Reducing dislocation formation in semiconductor devices through targeted carbon implantation 失效
    通过目标碳注入减少半导体器件中的位错形成

    公开(公告)号：US08343825B2

    公开(公告)日：2013-01-01

    申请号：US13009020

    申请日：2011-01-19

    申请人： Anthony G. Domenicucci ,  Shreesh Narasimha ,  Karen A. Nummy ,  Viorel C. Ontalus ,  Yun-Yu Wang

    发明人： Anthony G. Domenicucci ,  Shreesh Narasimha ,  Karen A. Nummy ,  Viorel C. Ontalus ,  Yun-Yu Wang

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7847 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/6659 ,  H01L29/7833

    摘要： A method of forming a semiconductor device includes implanting an amorphizing species into a crystalline semiconductor substrate, the substrate having a transistor gate structure formed thereupon. Carbon is implanted into amorphized regions of the substrate, with specific implant conditions tailored such that the peak concentration of carbon species coincides with the end of the stacking faults, where the stacking faults are created during the recrystallization anneal. The implanted carbon pins partial dislocations so as to prevent the dislocations from disassociating from the end of the stacking faults and moving to a region in the substrate directly below the transistor gate structure. This removes the defects, which cause device leakage fail.

    摘要翻译： 形成半导体器件的方法包括将非晶化物质注入晶体半导体衬底中，所述衬底具有在其上形成的晶体管栅极结构。 碳被植入到基底的非晶化区域中，其特定的植入条件被定制，使得碳类的峰值浓度与堆垛层错的结束一致，其中在重结晶退火期间产生堆垛层错。 植入的碳引脚部分位错，以防止位错从堆垛层错的末端脱离，并移动到晶体管栅极结构正下方的衬底区域。 这消除了导致设备泄漏失败的缺陷。

    Method of reducing embedded SiGe loss in semiconductor device manufacturing
    4.
    发明授权
    Method of reducing embedded SiGe loss in semiconductor device manufacturing 有权
    降低半导体器件制造中嵌入式SiGe损耗的方法

    公开(公告)号：US07687338B2

    公开(公告)日：2010-03-30

    申请号：US11950572

    申请日：2007-12-05

    申请人： Sameer Jain ,  Shreesh Narasimha ,  Karen A. Nummy ,  Viorel Ontalus ,  Jang H. Sim

    发明人： Sameer Jain ,  Shreesh Narasimha ,  Karen A. Nummy ,  Viorel Ontalus ,  Jang H. Sim

    IPC分类号： H01L21/336

    CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848 ,  Y10S257/90

    摘要： Embodiments of the invention provide a method of forming embedded silicon germanium (eSiGe) in source and drain regions of a p-type field-effect-transistor (pFET) through a disposable spacer process; depositing a gap-filling layer directly on the eSiGe in the source and drain regions in a first process; depositing a layer of offset spacer material on top of the gap-filling layer in a second process different from the first process; etching the offset spacer material and the gap-filling layer, thus forming a set of offset spacers and exposing the eSiGe in the source and drain regions of the pFET; and finishing formation of the pFET.

    摘要翻译： 本发明的实施例提供了通过一次性间隔物工艺在p型场效应晶体管（pFET）的源区和漏区中形成嵌入硅锗（eSiGe）的方法; 在第一过程中在源极和漏极区域中的eSiGe上直接沉积间隙填充层; 在与第一工艺不同的第二工艺中，在间隙填充层的顶部上沉积一层偏移间隔物材料; 蚀刻偏移间隔物材料和间隙填充层，从而形成一组偏移间隔物并暴露p​​FET的源区和漏区中的eSiGe; 并完成pFET的形成。

    METHOD OF REDUCING EMBEDDED SIGE LOSS IN SEMICONDUCTOR DEVICE MANUFACTURING
    5.
    发明申请
    METHOD OF REDUCING EMBEDDED SIGE LOSS IN SEMICONDUCTOR DEVICE MANUFACTURING 有权
    减少半导体器件制造中嵌入信号损失的方法

    公开(公告)号：US20090148988A1

    公开(公告)日：2009-06-11

    申请号：US11950572

    申请日：2007-12-05

    申请人： Sameer Jain ,  Shreesh Narasimha ,  Karen A. Nummy ,  Viorel Ontalus ,  Jang H. Sim

    发明人： Sameer Jain ,  Shreesh Narasimha ,  Karen A. Nummy ,  Viorel Ontalus ,  Jang H. Sim

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848 ,  Y10S257/90

    摘要： Embodiments of the invention provide a method of forming embedded silicon germanium (eSiGe) in source and drain regions of a p-type field-effect-transistor (pFET) through a disposable spacer process; depositing a gap-filling layer directly on the eSiGe in the source and drain regions in a first process; depositing a layer of offset spacer material on top of the gap-filling layer in a second process different from the first process; etching the offset spacer material and the gap-filling layer, thus forming a set of offset spacers and exposing the eSiGe in the source and drain regions of the pFET; and finishing formation of the pFET.

    摘要翻译： 本发明的实施例提供了通过一次性间隔物工艺在p型场效应晶体管（pFET）的源区和漏区中形成嵌入硅锗（eSiGe）的方法; 在第一过程中在源极和漏极区域中的eSiGe上直接沉积间隙填充层; 在与第一工艺不同的第二工艺中，在间隙填充层的顶部上沉积一层偏移间隔物材料; 蚀刻偏移间隔物材料和间隙填充层，从而形成一组偏移间隔物并暴露p​​FET的源区和漏区中的eSiGe; 并完成pFET的形成。

    METHOD OF FABRICATING A DEVICE USING LOW TEMPERATURE ANNEAL PROCESSES, A DEVICE AND DESIGN STRUCTURE
    8.
    发明申请
    METHOD OF FABRICATING A DEVICE USING LOW TEMPERATURE ANNEAL PROCESSES, A DEVICE AND DESIGN STRUCTURE 有权
    使用低温退火工艺制造器件的方法，器件和设计结构

    公开(公告)号：US20120180010A1

    公开(公告)日：2012-07-12

    申请号：US13421400

    申请日：2012-03-15

    申请人： Anthony G. DOMENICUCCI ,  Terence L. Kane ,  Shreesh Narasimha ,  Karen A. Nummy ,  Viorel Ontalus ,  Yun-Yu Wang

    发明人： Anthony G. DOMENICUCCI ,  Terence L. Kane ,  Shreesh Narasimha ,  Karen A. Nummy ,  Viorel Ontalus ,  Yun-Yu Wang

    IPC分类号： G06F17/50

    CPC分类号： H01L21/324 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7847

    摘要： A method of fabricating a device using a sequence of annealing processes is provided. More particularly, a logic NFET device fabricated using a low temperature anneal to eliminate dislocation defects, method of fabricating the NFET device and design structure is shown and described. The method includes forming a stress liner over a gate structure and subjecting the gate structure and stress liner to a low temperature anneal process to form a stacking force in single crystalline silicon near the gate structure as a way to memorized the stress effort. The method further includes stripping the stress liner from the gate structure and performing an activation anneal at high temperature on device.

    摘要翻译： 提供了使用退火处理序列制造器件的方法。 更具体地，示出并描述了使用低温退火制造以消除位错缺陷的逻辑NFET器件，制造NFET器件的方法和设计结构。 该方法包括在栅极结构上形成应力衬垫，并对栅极结构和应力衬垫进行低温退火处理，以在栅极结构附近的单晶硅中形成堆叠力，作为记忆应力的方法。 该方法还包括从栅极结构剥离应力衬垫并在器件上在高温下进行激活退火。

    METHOD FOR REDUCING TOP NOTCHING EFFECTS IN PRE-DOPED GATE STRUCTURES
    9.
    发明申请
    METHOD FOR REDUCING TOP NOTCHING EFFECTS IN PRE-DOPED GATE STRUCTURES 审中-公开
    用于减少前浇口结构中顶部止点效应的方法

    公开(公告)号：US20080188089A1

    公开(公告)日：2008-08-07

    申请号：US11671668

    申请日：2007-02-06

    申请人： Anthony I. Chou ,  Sadanand V. Deshpande ,  Renee T. Mo ,  Shreesh Narasimha ,  Katsunori Onishi ,  Dominic Schepis

    发明人： Anthony I. Chou ,  Sadanand V. Deshpande ,  Renee T. Mo ,  Shreesh Narasimha ,  Katsunori Onishi ,  Dominic Schepis

    IPC分类号： H01L21/31

    CPC分类号： H01L21/32105 ,  H01L21/28035 ,  H01L21/28247

    摘要： A method for reducing top notching effects in pre-doped gate structures includes subjecting an etched, pre-doped gate stack structure to a re-oxidation process, the re-oxidation process comprising a radical assisted re-oxidation process so as to result in the formation of an oxide layer over vertical sidewall and horizontal top surfaces of the etched gate stack structure. The resulting oxide layer has a substantially uniform thickness independent of grain boundary orientations of the gate stack structure and independent of the concentration and location of dopant material present therein.

    摘要翻译： 用于减少预掺杂栅极结构中的顶部切口效应的方法包括将经蚀刻的预掺杂栅极堆叠结构进行再氧化处理，所述再氧化工艺包括自由基辅助再氧化工艺，以便导致 在蚀刻的栅堆叠结构的垂直侧壁和水平顶表面上形成氧化物层。 所得到的氧化物层具有与栅极堆叠结构的晶界取向无关的基本均匀的厚度，而与其中存在的掺杂剂材料的浓度和位置无关。