Flexible configuration logic array block for programmable logic devices
    1.
    发明授权
    Flexible configuration logic array block for programmable logic devices 失效
    用于可编程逻辑器件的灵活配置逻辑阵列块

    公开(公告)号:US5341044A

    公开(公告)日:1994-08-23

    申请号:US49064

    申请日:1993-04-19

    IPC分类号: H03K19/173

    CPC分类号: H03K19/1737

    摘要: A programmable logic device has a number of dedicated global control input lines which interface directly with individual building blocks known as logic array blocks. These lines can be used for clocks, presets, clears, or output-enables. Other logic signal lines from the centrally located global interconnect array are selected through an array of multiplexers and then interface with the logic array block. A configuration array of multiplexers in the logic array block selects from among these inputs, generating local control input signals, the final functions of which are decided by further multiplexing at the macrocell level within the logic array block.

    摘要翻译: 可编程逻辑器件具有多个专用的全局控制输入线,其直接与被称为逻辑阵列块的各个构建块直接连接。 这些线可用于时钟,预设,清零或输出使能。 来自中心位置的全局互连阵列的其他逻辑信号线通过多路复用器阵列进行选择,然后与逻辑阵列块进行接口。 逻辑阵列块中的多路复用器的配置阵列从这些输入中选择产生本地控制输入信号,其最终功能通过在逻辑阵列块内的宏单元级进一步复用来确定。

    Programmable logic device having fast programmable logic array blocks
and a central global interconnect array
    2.
    发明授权
    Programmable logic device having fast programmable logic array blocks and a central global interconnect array 失效
    具有快速可编程逻辑阵列块和中央全局互连阵列的可编程逻辑器件

    公开(公告)号:US5473266A

    公开(公告)日:1995-12-05

    申请号:US324860

    申请日:1994-10-18

    IPC分类号: H03K19/173 H03K19/177

    CPC分类号: H03K19/1737

    摘要: A programmable logic device has a number of dedicated global control input lines which interface directly with individual building blocks known as logic array blocks. These lines can be used for clocks, presets, clears, or output-enables. Other logic signal lines from the centrally located global interconnect array are selected through an array of multiplexers and then interface with the logic array block. A configuration array of multiplexers in the logic array block selects from among these inputs, generating local control input signals, the final functions of which are decided by further multiplexing at the macrocell level within the logic array block.

    摘要翻译: 可编程逻辑器件具有多个专用的全局控制输入线,其直接与被称为逻辑阵列块的各个构建块直接连接。 这些线可用于时钟,预设,清零或输出使能。 来自中心位置的全局互连阵列的其他逻辑信号线通过多路复用器阵列进行选择,然后与逻辑阵列块进行接口。 逻辑阵列块中的多路复用器的配置阵列从这些输入中选择产生本地控制输入信号,其最终功能通过在逻辑阵列块内的宏单元级进一步复用来确定。

    High speed, low power macrocell
    3.
    发明授权
    High speed, low power macrocell 失效
    高速,低功率的宏单元

    公开(公告)号:US5523706A

    公开(公告)日:1996-06-04

    申请号:US401046

    申请日:1995-03-08

    IPC分类号: H03K19/173 H03K19/177

    CPC分类号: H03K19/17716 H03K19/1736

    摘要: A macrocell for use in a programmable logic device (PLD) providing for enhanced logic capability and reduced setup time. The preferred embodiment of the macrocell includes two look-up tables, for increased fan-in, and two flip-flops that increase fan-out, thereby doubling logic capability of the PLD without unacceptably increasing device size. Doubling the register count makes this PLD particularly suitable for applications employing high density sequential logic. Furthermore, a second register can be used for receiving fast input signals form an input to the PLD to reduce setup time.

    摘要翻译: 用于可编程逻辑器件(PLD)的宏单元,提供增强的逻辑能力和缩短的建立时间。 宏单元的优选实施例包括用于增加扇入的两个查找表,以及增加扇出的两个触发器,从而使PLD的逻辑能力加倍,而不增加设备大小。 将寄存器数量加倍使得该PLD特别适用于采用高密度序列逻辑的应用。 此外,第二寄存器可用于从PLD的输入接收快速输入信号以减少建立时间。

    Macrocell comprised of two look-up tables and two flip-flops
    4.
    发明授权
    Macrocell comprised of two look-up tables and two flip-flops 失效
    宏单元由两个查找表和两个触发器组成

    公开(公告)号:US5399922A

    公开(公告)日:1995-03-21

    申请号:US086420

    申请日:1993-07-02

    IPC分类号: H03K19/173 H03K19/177

    CPC分类号: H03K19/17716 H03K19/1736

    摘要: A macrocell for use in a programmable logic device (PLD) providing for enhanced logic capability and reduced setup time. The preferred embodiment of the macrocell includes two look-up tables, for increased fan-in, and two flip-flops that increase fan-out, thereby doubling logic capability of the PLD without unacceptably increasing device size. Doubling the register count makes this PLD particularly suitable for applications employing high density sequential logic. Furthermore, a second register can be used for receiving fast input signals form an input to the PLD to reduce setup time.

    摘要翻译: 用于可编程逻辑器件(PLD)的宏单元,提供增强的逻辑能力和缩短的建立时间。 宏单元的优选实施例包括用于增加扇入的两个查找表,以及增加扇出的两个触发器,从而使PLD的逻辑能力加倍,而不增加设备大小。 将寄存器数量加倍使得该PLD特别适用于采用高密度序列逻辑的应用。 此外,第二寄存器可用于从PLD的输入接收快速输入信号以减少建立时间。

    Method and apparatus for reducing the number of programmable
architecture elements required for implementing a look-up table in a
programmable logic device
    5.
    发明授权
    Method and apparatus for reducing the number of programmable architecture elements required for implementing a look-up table in a programmable logic device 失效
    用于减少在可编程逻辑器件中实现查找表所需的可编程架构元件的数量的方法和装置

    公开(公告)号:US5953537A

    公开(公告)日:1999-09-14

    申请号:US259360

    申请日:1994-06-14

    IPC分类号: H03K19/173 H03K19/00

    CPC分类号: H03K19/1736

    摘要: A method and apparatus for reducing the number of programmable architecture elements required for implementing a look-up table in a programmable logic device. At least one logic function to be performed by the look-up table is chosen. An output state is determined for each set of inputs to the look-up table, the output state being an array of outputs of the look-up table. Each output state is made up of responses of the chosen logic functions to a particular set of input variables. Identical output states are formed into groups. Selected groups of the output states which do not require programmable architecture elements are eliminated. A programmable architecture element is then assigned for each remaining group of output states.

    摘要翻译: 一种用于减少在可编程逻辑器件中实现查找表所需的可编程架构元件的数量的方法和装置。 选择由查找表执行的至少一个逻辑功能。 针对查找表的每组输入确定输出状态,输出状态是查找表的输出数组。 每个输出状态由所选择的逻辑功能对特定输入变量集合的响应组成。 相同的输出状态形成组。 消除了不需要可编程架构元件的选择的输出状态组。 然后为每个剩余的输出状态组分配可编程架构元素。