公开(公告)号：US5473266A

公开(公告)日：1995-12-05

申请号：US324860

申请日：1994-10-18

申请人： Bahram Ahanin ,  Janusz K. Balicki ,  Khusrow Kiani ,  William Leong ,  Ken-Ming Li ,  Bezhad Nouban

发明人： Bahram Ahanin ,  Janusz K. Balicki ,  Khusrow Kiani ,  William Leong ,  Ken-Ming Li ,  Bezhad Nouban

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/1737

摘要： A programmable logic device has a number of dedicated global control input lines which interface directly with individual building blocks known as logic array blocks. These lines can be used for clocks, presets, clears, or output-enables. Other logic signal lines from the centrally located global interconnect array are selected through an array of multiplexers and then interface with the logic array block. A configuration array of multiplexers in the logic array block selects from among these inputs, generating local control input signals, the final functions of which are decided by further multiplexing at the macrocell level within the logic array block.

摘要翻译： 可编程逻辑器件具有多个专用的全局控制输入线，其直接与被称为逻辑阵列块的各个构建块直接连接。 这些线可用于时钟，预设，清零或输出使能。 来自中心位置的全局互连阵列的其他逻辑信号线通过多路复用器阵列进行选择，然后与逻辑阵列块进行接口。 逻辑阵列块中的多路复用器的配置阵列从这些输入中选择产生本地控制输入信号，其最终功能通过在逻辑阵列块内的宏单元级进一步复用来确定。

公开(公告)号：US5341044A

公开(公告)日：1994-08-23

申请号：US49064

申请日：1993-04-19

申请人： Bahram Ahanin ,  Janusz K. Balicki ,  Khusrow Kiani ,  William Leong ,  Ken-Ming Li ,  Bezhad Nouban

发明人： Bahram Ahanin ,  Janusz K. Balicki ,  Khusrow Kiani ,  William Leong ,  Ken-Ming Li ,  Bezhad Nouban

IPC分类号： H03K19/173

CPC分类号： H03K19/1737

摘要： A programmable logic device has a number of dedicated global control input lines which interface directly with individual building blocks known as logic array blocks. These lines can be used for clocks, presets, clears, or output-enables. Other logic signal lines from the centrally located global interconnect array are selected through an array of multiplexers and then interface with the logic array block. A configuration array of multiplexers in the logic array block selects from among these inputs, generating local control input signals, the final functions of which are decided by further multiplexing at the macrocell level within the logic array block.

摘要翻译： 可编程逻辑器件具有多个专用的全局控制输入线，其直接与被称为逻辑阵列块的各个构建块直接连接。 这些线可用于时钟，预设，清零或输出使能。 来自中心位置的全局互连阵列的其他逻辑信号线通过多路复用器阵列进行选择，然后与逻辑阵列块进行接口。 逻辑阵列块中的多路复用器的配置阵列从这些输入中选择产生本地控制输入信号，其最终功能通过在逻辑阵列块内的宏单元级进一步复用来确定。

公开(公告)号：US5953537A

公开(公告)日：1999-09-14

申请号：US259360

申请日：1994-06-14

申请人： Janusz K. Balicki ,  Bezhad Nouban ,  Khusrow Kiani

发明人： Janusz K. Balicki ,  Bezhad Nouban ,  Khusrow Kiani

IPC分类号： H03K19/173 ,  H03K19/00

CPC分类号： H03K19/1736

摘要： A method and apparatus for reducing the number of programmable architecture elements required for implementing a look-up table in a programmable logic device. At least one logic function to be performed by the look-up table is chosen. An output state is determined for each set of inputs to the look-up table, the output state being an array of outputs of the look-up table. Each output state is made up of responses of the chosen logic functions to a particular set of input variables. Identical output states are formed into groups. Selected groups of the output states which do not require programmable architecture elements are eliminated. A programmable architecture element is then assigned for each remaining group of output states.

摘要翻译： 一种用于减少在可编程逻辑器件中实现查找表所需的可编程架构元件的数量的方法和装置。 选择由查找表执行的至少一个逻辑功能。 针对查找表的每组输入确定输出状态，输出状态是查找表的输出数组。 每个输出状态由所选择的逻辑功能对特定输入变量集合的响应组成。 相同的输出状态形成组。 消除了不需要可编程架构元件的选择的输出状态组。 然后为每个剩余的输出状态组分配可编程架构元素。