公开(公告)号：US08868633B2

公开(公告)日：2014-10-21

申请号：US13436555

申请日：2012-03-30

申请人： Carl E. Lemonds ,  Jay E. Fleischman ,  David M. Russinoff

发明人： Carl E. Lemonds ,  Jay E. Fleischman ,  David M. Russinoff

IPC分类号： G06F7/552

CPC分类号： G06F1/03 ,  G06F7/5525 ,  G06F2101/08 ,  G06F2207/5528

摘要： A method, performed by a processor, of determining a square root using a single processor cycle per iteration is described. The method includes, in a single cycle: obtaining, from a stored lookup table, a quotient digit and a square of the quotient digit; retrieving a current solution; and determining a new solution using the current solution and the quotient digit. Circuitry configured to perform the method is described.

摘要翻译： 描述了由处理器执行的使用每个迭代的单个处理器周期来确定平方根的方法。 该方法在单个周期中包括：从存储的查找表中获得商数和商数的平方; 检索当前解决方案; 并使用当前解和商数确定新解。 描述配置为执行该方法的电路。

公开(公告)号：US20120191952A1

公开(公告)日：2012-07-26

申请号：US13011637

申请日：2011-01-21

申请人： Jay E. FLEISCHMAN ,  Matthew M. CRUM ,  Kelvin GOVEAS ,  Michael D. ESTLICK ,  Barry J. ARNOLD ,  Ranganathan SUDHAKAR ,  Betty A. MCDANIEL

发明人： Jay E. FLEISCHMAN ,  Matthew M. CRUM ,  Kelvin GOVEAS ,  Michael D. ESTLICK ,  Barry J. ARNOLD ,  Ranganathan SUDHAKAR ,  Betty A. MCDANIEL

IPC分类号： G06F9/318 ,  G06F9/30

CPC分类号： G06F9/30094 ,  G06F9/30109 ,  G06F9/30192 ,  G06F9/384

摘要： Methods and apparatuses are provided for increased efficiency and enhanced power saving in a processor via scalar code optimization. The method comprises determining that an instruction comprises a scalar instruction and then processing the instruction using only a lower portion of an XMM register. The apparatus comprises an operational unit capable of determining whether an instruction comprises a scalar instruction and execution units responsive that determining for processing the scalar instruction using only a lower portion of an XMM register of the processor. By not processing the upper portion of the XMM register efficiency is increased and power saving is enhanced.

摘要翻译： 提供了通过标量代码优化在处理器中提高效率和增强功率节省的方法和装置。 该方法包括确定指令包括标量指令，然后仅使用XMM寄存器的下部来处理该指令。 所述装置包括能够确定指令是否包括标量指令的操作单元，并且所述执行单元响应于仅使用所述处理器的XMM寄存器的下部来确定所述标量指令的处理。 通过不处理XMM寄存器的上部部分，效率提高，省电。

公开(公告)号：US20120166769A1

公开(公告)日：2012-06-28

申请号：US12979946

申请日：2010-12-28

申请人： Jay E. Fleischman ,  Ranganathan Sudhakar

发明人： Jay E. Fleischman ,  Ranganathan Sudhakar

IPC分类号： G06F9/40 ,  G06F9/38

CPC分类号： G06F9/3838 ,  G06F9/3017

摘要： Methods and apparatuses are provided for achieving increased performance via elimination of serial dependencies in instructions or instruction sequences. The apparatus comprises an operational unit for determining whether an instruction will cause dependencies during completion in an execution unit. Responsive to that determination the instruction is replaced with an alternative instruction for completion in the execution unit. In this way, the alternative instruction is completed without causing dependencies in the execution unit. The method comprises determining that an instruction will cause dependencies during completion in a processor and replacing the instruction with an alternative instruction for completion in the processor.

摘要翻译： 提供了通过消除指令或指令序列中的串行依赖性来实现提高性能的方法和装置。 该装置包括用于在执行单元中完成期间确定指令是否将引起依赖性的操作单元。 响应于该确定，指令被替换为在执行单元中完成的替代指令。 以这种方式，完成替代指令而不会在执行单元中引起相关性。 该方法包括确定在处理器完成期间指令将引起相关性，并用替代指令替换指令以在处理器中完成。

公开(公告)号：US06550023B1

公开(公告)日：2003-04-15

申请号：US09175010

申请日：1998-10-19

申请人： Jeffery C. Brauch ,  Jay E. Fleischman

发明人： Jeffery C. Brauch ,  Jay E. Fleischman

IPC分类号： G06F1100

CPC分类号： G11C29/44 ,  G11C29/40 ,  G11C2029/0405 ,  G11C2029/1208 ,  G11C2029/1802 ,  G11C2029/2602

摘要： A method and apparatus for locating defects in an on-chip memory of an integrated circuit is presented. During a memory test of on-chip memory, a known data value is written to a word in the on-chip memory, and an output data value is read back from the same addressed word in memory. A comparison of the output data value and expected data value is performed within the integrated circuit, producing a comparison result indicating which of the bit cells in the addressed word have failed. The address and comparison result are transferred external to said integrated circuit and correspond to a bitmap entry in a bitmap. The execution of a full memory test results in a complete bitmap indicating all the failed cells of the on-chip memory.

摘要翻译： 提出了一种用于定位集成电路的片上存储器中的缺陷的方法和装置。 在片上存储器的存储器测试期间，将已知数据值写入片上存储器中的字，并且从存储器中的相同寻址字读出输出数据值。 在集成电路内执行输出数据值和期望数据值的比较，产生指示寻址字中哪个位单元失败的比较结果。 地址和比较结果在外部传送到所述集成电路，并对应于位图中的位图条目。 执行完整的内存测试会产生一个完整的位图，指示片内存储器的所有故障单元。

公开(公告)号：US6141779A

公开(公告)日：2000-10-31

申请号：US175032

申请日：1998-10-19

申请人： J. Michael Hill ,  Jay E. Fleischman

发明人： J. Michael Hill ,  Jay E. Fleischman

IPC分类号： G11C29/00

CPC分类号： G11C29/802 ,  G11C29/835 ,  G11C29/848

摘要： A novel method and apparatus for automatically programming a redundancy map for a circuit is presented. A circuit comprising a plurality of identical reconfigurable circuit elements and a redundant circuit element includes a redundancy map register which may be programmed to allow faulty circuit elements to be deactivated and bypassed and the redundant circuit element to be activated. A fault detector tests the circuit to generate a fault indicator indicating which one of the reconfigurable circuit elements is a faulty circuit element. An encoder encodes the fault indicator into an encoded fault indicator. A decoder decodes the encoded fault indicator to generate a redundancy map for configuring the reconfigurable circuit elements.

摘要翻译： 介绍了一种用于自动编程电路冗余映射的方法和装置。 包括多个相同的可重新配置电路元件和冗余电路元件的电路包括冗余映射寄存器，该冗余映射寄存器可被编程为允许故障电路元件被去激活和旁路，并且所述冗余电路元件被激活。 故障检测器测试电路以产生故障指示器，指示哪一个可重构电路元件是故障电路元件。 编码器将故障指示器编码为编码故障指示器。 解码器对编码的故障指示符进行解码以产生用于配置可重构电路元件的冗余映射。

公开(公告)号：US20130262541A1

公开(公告)日：2013-10-03

申请号：US13436555

申请日：2012-03-30

申请人： Carl E. Lemonds ,  Jay E. Fleischman ,  David M. Russinoff

发明人： Carl E. Lemonds ,  Jay E. Fleischman ,  David M. Russinoff

IPC分类号： G06F1/03

CPC分类号： G06F1/03 ,  G06F7/5525 ,  G06F2101/08 ,  G06F2207/5528

摘要： A method, performed by a processor, of determining a square root using a single processor cycle per iteration is described. The method includes, in a single cycle: obtaining, from a stored lookup table, a quotient digit and a square of the quotient digit; retrieving a current solution; and determining a new solution using the current solution and the quotient digit. Circuitry configured to perform the method is described.

摘要翻译： 描述了由处理器执行的使用每个迭代的单个处理器周期来确定平方根的方法。 该方法在单个周期中包括：从存储的查找表中获得商数和商数的平方; 检索当前解决方案; 并使用当前解和商数确定新解。 描述配置为执行该方法的电路。

公开(公告)号：US20130007418A1

公开(公告)日：2013-01-03

申请号：US13174293

申请日：2011-06-30

申请人： Jay E. Fleischman ,  Emil Talpes ,  Debjit DasSarma

发明人： Jay E. Fleischman ,  Emil Talpes ,  Debjit DasSarma

IPC分类号： G06F9/30

CPC分类号： G06F9/3865

摘要： Methods and apparatuses are provided for flush operations in a processor. The apparatus comprises an out-of-order execution unit for processing instructions issued in-order from an instruction decoder for first and second threads and being configured to identify an errored instruction in a first thread. A retire unit includes a retire queue for receiving completed instructions from the out-of-order execution unit, the retire unit being configured retire older in-order first thread instructions until the errored instruction would be the next instruction to be retired, and then flushing the errored instruction and all later in-order first thread instructions from the retire queue. The method comprises determining that an errored instruction is being processed by an out-of-order execution unit of a processor and continuing to process to completion instructions earlier in-order from the errored instruction until the completion of the errored instruction. Following completion of the errored instruction, it is flushed along with all instructions later in-order than the errored instruction to recover the processor to a pre-error state.

摘要翻译： 为处理器中的冲洗操作提供了方法和装置。 该装置包括用于处理从第一和第二线程的指令解码器按顺序发出的指令的无序执行单元，并且被配置为识别第一线程中的错误指令。 退休单元包括用于从无序执行单元接收完成的指令的退出队列，所述退休单元被配置为退出旧的有序第一线程指令，直到错误的指令将是下一个待退出的指令，然后冲洗 错误的指令和所有后续排序的第一线程指令从退出队列。 所述方法包括：确定处理器的无序执行单元正在处理错误指令，并且继续处理从错误指令到故障指令完成之前的先前完成指令。 完成错误指令之后，随着所有指令的刷新顺序都会比错误的指令进行刷新，以将处理器恢复到预错误状态。

公开(公告)号：US09268575B2

公开(公告)日：2016-02-23

申请号：US13174293

申请日：2011-06-30

申请人： Jay E. Fleischman ,  Emil Talpes ,  Debjit DasSarma

发明人： Jay E. Fleischman ,  Emil Talpes ,  Debjit DasSarma

IPC分类号： G06F9/38

CPC分类号： G06F9/3865

摘要： Methods and apparatuses are provided for flush operations in a processor. The apparatus comprises an out-of-order execution unit for processing instructions issued in-order from an instruction decoder for first and second threads and being configured to identify an errored instruction in a first thread. A retire unit includes a retire queue for receiving completed instructions from the out-of-order execution unit, the retire unit being configured retire older in-order first thread instructions until the errored instruction would be the next instruction to be retired, and then flushing the errored instruction and all later in-order first thread instructions from the retire queue. The method comprises determining that an errored instruction is being processed by an out-of-order execution unit of a processor and continuing to process to completion instructions earlier in-order from the errored instruction until the completion of the errored instruction. Following completion of the errored instruction, it is flushed along with all instructions later in-order than the errored instruction to recover the processor to a pre-error state.

摘要翻译： 为处理器中的冲洗操作提供了方法和装置。 该装置包括用于处理从第一和第二线程的指令解码器按顺序发出的指令的无序执行单元，并且被配置为识别第一线程中的错误指令。 退休单元包括用于从无序执行单元接收完成的指令的退出队列，退休单元被配置为退出较旧的有序第一线程指令，直到错误的指令将是下一个要退出的指令，然后冲洗 错误的指令和所有后续排序的第一线程指令从退出队列。 所述方法包括：确定处理器的无序执行单元正在处理错误指令，并且继续处理从错误指令到故障指令完成之前的先前完成指令。 完成错误指令之后，随着所有指令的刷新顺序都会比错误的指令进行刷新，以将处理器恢复到预错误状态。