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1.发明授权Division with rectangular multiplier supporting multiple precisions and operand types 有权具有矩形乘法器的分支，支持多种精度和操作数类型公开(公告)号：US07962543B2
公开(公告)日：2011-06-14
申请号：US11756885
申请日：2007-06-01
IPC分类号： G06F7/535
CPC分类号： G06F7/4873 , G06F2207/5356
摘要： A division method includes determining a precision indicator for the division operation that indicates whether the quotient should be a single precision, double precision, or extended precision floating-point number. The division is performed at a rectangular multiplier using the Goldschmidt or Newton-Raphson algorithm. Each algorithm calculates one or more intermediate values in order to determine the quotient. For example, the Goldschmidt algorithm calculates a complement of a product of the dividend and an estimate of the reciprocal of the divisor. The quotient is determined based on a portion of one or more of these intermediate values. Because only a portion of the intermediate value is used, the division can be performed efficiently at the rectangular multiplier, and therefore the quotient can be determined more quickly and still achieve the desired level of precision.
摘要翻译： 分割方法包括确定用于指示商是否应当是单精度，双精度或扩展精度浮点数的除法运算的精度指示符。 使用Goldschmidt或Newton-Raphson算法在矩形乘法器上执行除法。 每个算法计算一个或多个中间值以确定商。 例如，Goldschmidt算法计算股息的乘积的互补和除数的倒数的估计。 基于这些中间值中的一个或多个的一部分来确定商。 因为仅使用中间值的一部分，所以可以在矩形乘法器上有效地执行除法，因此可以更快速地确定商并且仍然达到期望的精度水平。
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2.发明授权公开(公告)号：US06256724B1
公开(公告)日：2001-07-03
申请号：US09244674
申请日：1999-02-04
IPC分类号： G06F1316
CPC分类号： G06F9/3879 , G06F9/3897
摘要： A data processing system includes a digital signal processor core and a co-processor. The co-processor has a local memory within the address space of the said digital signal processor core. The co-processor responds commands from the digital signal processor core. A direct memory access circuit autonomously transfers data to and from the local memory of the co-processor. Co-processor commands are stored in a command FIFO memory mapped to a predetermined memory address. Control commands includes a receive data synchronism command stalling the co-processor until completion of a memory transfer into the local memory. A send data synchronism command causes the co-processor to signal the direct memory access circuit to trigger memory transfer out of the local memory. An interrupt command causes the co-processor to interrupt the digital signal processor core.
摘要翻译： 数据处理系统包括数字信号处理器核和协处理器。 协处理器在所述数字信号处理器核心的地址空间内具有本地存储器。 协处理器响应来自数字信号处理器核心的命令。 直接存储器访问电路自主地将数据传送到协处理器的本地存储器和/或从协处理器的本地存储器传送数据。 协处理器命令存储在映射到预定存储器地址的命令FIFO存储器中。 控制命令包括停止协处理器的接收数据同步命令，直到完成到本地存储器的存储器传送。 发送数据同步命令使协处理器向直接存储器访问电路发出信号，以触发从本地存储器传出的存储器。 中断命令使协处理器中断数字信号处理器内核。
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公开(公告)号：US08868633B2
公开(公告)日：2014-10-21
申请号：US13436555
申请日：2012-03-30
IPC分类号： G06F7/552
CPC分类号： G06F1/03 , G06F7/5525 , G06F2101/08 , G06F2207/5528
摘要： A method, performed by a processor, of determining a square root using a single processor cycle per iteration is described. The method includes, in a single cycle: obtaining, from a stored lookup table, a quotient digit and a square of the quotient digit; retrieving a current solution; and determining a new solution using the current solution and the quotient digit. Circuitry configured to perform the method is described.
摘要翻译： 描述了由处理器执行的使用每个迭代的单个处理器周期来确定平方根的方法。 该方法在单个周期中包括：从存储的查找表中获得商数和商数的平方; 检索当前解决方案; 并使用当前解和商数确定新解。 描述配置为执行该方法的电路。
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公开(公告)号：US20130262541A1
公开(公告)日：2013-10-03
申请号：US13436555
申请日：2012-03-30
IPC分类号： G06F1/03
CPC分类号： G06F1/03 , G06F7/5525 , G06F2101/08 , G06F2207/5528
摘要： A method, performed by a processor, of determining a square root using a single processor cycle per iteration is described. The method includes, in a single cycle: obtaining, from a stored lookup table, a quotient digit and a square of the quotient digit; retrieving a current solution; and determining a new solution using the current solution and the quotient digit. Circuitry configured to perform the method is described.
摘要翻译： 描述了由处理器执行的使用每个迭代的单个处理器周期来确定平方根的方法。 该方法在单个周期中包括：从存储的查找表中获得商数和商数的平方; 检索当前解决方案; 并使用当前解和商数确定新解。 描述配置为执行该方法的电路。
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5.发明授权公开(公告)号：US06611857B1
公开(公告)日：2003-08-26
申请号：US09713583
申请日：2000-11-15
申请人： Carl E. Lemonds , Alan Gatherer
发明人： Carl E. Lemonds , Alan Gatherer
IPC分类号： G06F752
CPC分类号： G06F7/5318 , G06F1/3203 , G06F1/3237 , G06F1/3243 , G06F1/3287 , G06F7/5338 , Y02D10/128 , Y02D10/152 , Y02D10/171
摘要： A multiplier (12) is disclosed that includes an encoder (36), a hierarchy of compressors (40, 42, 44, 50, 52, 60 and 70), a bit detector (130) and a switch (134). The encoder (36) is operable to receive a first and second encoder input. The compressors (40, 42, 44, 50, 52, 60 and 70) are coupled to the encoder (36). The compressors (40,42, 44, 50, 52, 60 and 70) are operable to receive a first number of inputs and to generate a second number of outputs, with the second number being less than the first number. The bit detector (130) is operable to monitor the first encoder input to determine whether the first encoder input is in a reduced precision range (28). The bit detector (130) is also operable to deactivate a subset of the compressors (40 and 50) when the bit detector (130) determines that the first encoder input is in the reduced precision range (28). The switch (134) is coupled to a specified one of the compressors (42). The switch (134) is operable to redirect the path of one of the outputs for the specified compressor (42) such that the subset of the compressors (40 and 50) is removed from the path when the bit detector (130) determines that the first encoder input is in the reduced precision range (28).
摘要翻译： 公开了一种乘法器（12），其包括编码器（36），压缩机层级（40,42,44,50,52,60和70），位检测器（130）和开关（134）。 编码器（36）可操作以接收第一和第二编码器输入。 压缩机（40,42,44,50,52,60和70）联接到编码器（36）。 压缩机（40,42,44,50,52,60和70）可操作以接收第一数量的输入并产生第二数量的输出，其中第二数量小于第一数量。 位检测器（130）可操作以监视第一编码器输入以确定第一编码器输入是否处于减小的精度范围（28）。 当位检测器（130）确定第一编码器输入处于降低的精度范围（28）时，位检测器（130）还可操作以停用压缩机（40和50）的子集。 开关（134）耦合到指定的一个压缩机（42）。 开关（134）可操作以重定向用于指定的压缩机（42）的输出之一的路径，使得当位检测器（130）确定压缩机（40）和（50）的子集 第一个编码器输入处于减小的精度范围（28）。
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6.发明申请DIVISION WITH RECTANGULAR MULTIPLIER SUPPORTING MULTIPLE PRECISIONS AND OPERAND TYPES 有权具有矩形多用户支持多种精度和操作类型的部分公开(公告)号：US20080301213A1
公开(公告)日：2008-12-04
申请号：US11756885
申请日：2007-06-01
IPC分类号： G06F7/483
CPC分类号： G06F7/4873 , G06F2207/5356
摘要： A division method includes determining a precision indicator for the division operation that indicates whether the quotient should be a single precision, double precision, or extended precision floating-point number. The division is performed at a rectangular multiplier using the Goldschmidt or Newton-Raphson algorithm. Each algorithm calculates one or more intermediate values in order to determine the quotient. For example, the Goldschmidt algorithm calculates a complement of a product of the dividend and an estimate of the reciprocal of the divisor. The quotient is determined based on a portion of one or more of these intermediate values. Because only a portion of the intermediate value is used, the division can be performed efficiently at the rectangular multiplier, and therefore the quotient can be determined more quickly and still achieve the desired level of precision.
摘要翻译： 分割方法包括确定用于指示商是否应当是单精度，双精度或扩展精度浮点数的除法运算的精度指示符。 使用Goldschmidt或Newton-Raphson算法在矩形乘法器上执行除法。 每个算法计算一个或多个中间值以确定商。 例如，Goldschmidt算法计算股息的乘积的互补和除数的倒数的估计。 基于这些中间值中的一个或多个的一部分来确定商。 因为仅使用中间值的一部分，所以可以在矩形乘法器上有效地执行除法，因此可以更快速地确定商并且仍然达到期望的精度水平。
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公开(公告)号：US06298366B1
公开(公告)日：2001-10-02
申请号：US09244973
申请日：1999-02-04
IPC分类号： G06F748
CPC分类号： G06F7/5443
摘要： A reconfigurable co-processor adapted for multiple multiply-accumulate operations includes plural pairs of multipliers, plural first adders receiving respective product outputs from a pairs of multipliers, and at least one second adder receiving sum outputs from a corresponding pair of first adders. The co-processor includes sign extend circuits at the output of each multiplier. One multiplier of each pair has a fixed left shift circuit that left shifts the product output a predetermined number of bits. The other multiplier in each pair includes a right shift circuit that right shifts the product output the number of bits. Multiplexers at the output of the first multiplier in each pair select the sign extended or the left shifted products. Multiplexers at the output of the second multiplier in each pair select the product, the right shifted product or pass through the inputs. The sign extend circuit for the second multiplier follows the multiplexer. Third adders receive the sum outputs of the second adders and produce a third sum output. These third adders include plural selectable output accumulators and variable right shifter at their outputs. The third adders may separately sum the product sums from four multipliers each. Alternatively, the third adders may accumulate the products of eight multipliers.
摘要翻译： 适用于多重乘法运算的可重配置协处理器包括多对乘法器，多个第一加法器，从一对乘法器接收相应的乘积输出，以及至少一个第二加法器，从相应的第一加法器对接收和输出。 协处理器在每个乘法器的输出端包括符号扩展电路。 每对的一个乘法器具有固定的左移位电路，其使乘积输出偏移预定数量的位。 每对中的另一个乘法器包括一个右移位电路，用于将乘积输出向右移位位数。 每对中第一乘法器输出端的多路复用器选择扩展符号或左移符号。 每对中第二乘法器输出端的多路复用器选择产品，右移产品或通过输入。 第二乘法器的符号扩展电路跟随多路复用器。 第三加法器接收第二加法器的和输出并产生第三和输出。 这些第三加法器在其输出端包括多个可选输出累加器和可变右移位器。 第三加法器可以分别将乘积和乘以四个乘法器。 或者，第三加法器可以累积八个乘法器的乘积。
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8.发明授权
公开(公告)号：US5889691A
公开(公告)日：1999-03-30
申请号：US782001
申请日：1997-01-06
申请人： Alan Gatherer , Carl E. Lemonds
发明人： Alan Gatherer , Carl E. Lemonds
IPC分类号： G06F7/52
CPC分类号： G06F7/5272
摘要： In a multiplier unit having a preprocessor stage, a multiplier stage, and a summation stage, the multiplier stage includes a shift register, a gate component for controllably transmitting the multiplicand A in a manner determined by a bit signal of multiplier B applied to the gate component control terminal. Partial products are grouped by multiplicand digits and each digit is applied, through delay components determined by the order of the digit, to first terminals of an associated adder components. Output signals from each adder component is transmitted through a plurality of delay components and applied to second input terminals of the same adder component. In this manner, partial products A.sub.p *B.sub.q are assembled and the partial products (A.sub.0 + . . . A.sub.M)*B.sub.q =A*B.sub.q can be applied to the summation unit in a single period. When the multiplier is an integer multiple of the multiplicand, the implementation is particularly convenient.
摘要翻译： 在具有预处理器级，乘法器级和求和级的乘法器单元中，乘法器级包括移位寄存器，用于以由施加到门的乘法器B的位信号确定的方式可控地发送被乘数A的门分量 组件控制终端。 部分产品按被乘数分组，每个数字通过由数字顺序确定的延迟分量应用于相关加法器分量的第一个终端。 来自每个加法器分量的输出信号通过多个延迟分量传输并被施加到相同加法器分量的第二输入端。 以这种方式，部分乘积Ap * Bq被组装，并且部分乘积（A0 +。。AM）* Bq = A * Bq可以在单个周期内应用于求和单元。 当乘数是被乘数的整数倍时，实现特别方便。
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公开(公告)号：US5646877A
公开(公告)日：1997-07-08
申请号：US451091
申请日：1995-05-25
CPC分类号： G06F7/5336
摘要： A multiplier and method of multiplying a multiplicand by a multiplier comprising providing a multiplicand of predetermined radix, preferably two, and a predetermined multiple of the multiplicand, preferably three, of the predetermined radix. First and second paths are provided, each path including the multiplicand and the multiple of the multiplicand. One of the multiplicand or multiple of the multiplicand in said first path is selected responsive to the value of the multiplier and one of the multiplicand or multiple of the multiplicand in the second path is selected responsive to the value of the multiplier. The selected multiplicand or multiple of the multiplicand in said first path is left shifted a number of shifts determined by the value of the multiplier and the selected multiplicand or multiple of the multiplicand in the second path is left shifted a number of shifts determined by the value of the multiplier. At least one of the shifted multiplicands or multiples thereof is then assigned one of a positive or negative value as determined by the value of the multiplier and the shifted values are then added together. The circuit also includes an encoder responsive to the value of the multiplier to control the selection of the multiplicand or multiple thereof, the left shifting and the assignment of a positive or negative value. The encoder can include a truth table to assist in performing this function.
摘要翻译： 将被乘数乘以乘法器的乘法器和方法，包括提供预定基数的预定基数，优选为两个的乘法器和预定倍数的预定倍数，优选地三个预定基数。 提供第一和第二路径，每个路径包括被乘数和被乘数的倍数。 响应于乘法器的值来选择所述第一路径中的被乘数之一或被乘数之一，并且响应于乘法器的值来选择第二路径中被乘数中的一个或多个被乘数中的一个。 在所述第一路径中所选择的被乘数或被乘数的倍数是由乘法器的值确定的移位量左移，并且所选择的被乘数或第二路径中被乘数的倍数向左移位由该值确定的多个移位 的乘数。 然后，其中移位的被乘数或其倍数中的至少一个被分配为由乘法器的值确定的正值或负值之一，然后将移位值相加。 电路还包括响应于乘法器的值以控制被乘数或其倍数的选择的编码器，左移位和正值或负值的分配。 编码器可以包括真值表以帮助执行该功能。
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