公开(公告)号：US5628637A

公开(公告)日：1997-05-13

申请号：US351848

申请日：1994-12-08

申请人： Victor Pecone ,  Jay Lory

发明人： Victor Pecone ,  Jay Lory

IPC分类号： G06F1/18 ,  H05K1/00 ,  H05K1/14 ,  H01R9/09

CPC分类号： G06F1/185 ,  G06F1/184 ,  G06F1/186 ,  H05K1/0286 ,  H05K1/141

摘要： A SCSI adapter card which provides one or more internal SCSI channels and includes connectors for an optional daughter card which provides an external SCSI connector. The daughter card is a parallel mezzanine style daughter board which provides modular and upgradable SCSI bus routing options. In the preferred embodiment, the adapter card includes two SCSI controllers which provide two internal SCSI channels. The daughter board can include up to 2 SCSI controllers for additional SCSI channels. The daughter board can reroute one or more of the internal SCSI channels to the external connector according to various SCSI routing options or can include one or more SCSI controllers for additional SCSI channels. In one embodiment, the daughter board does not include a SCSI controller, but rather serves to reroute one or more of the internal SCSI controllers to the external connector. In a second embodiment, the daughter board includes one or more SCSI controllers which provide external SCSI channels in addition to the internal SCSI channels. The incorporation of the external SCSI connector on the daughter board eliminates the need for the base PWA add-in card to include the external SCSI connector and also eliminates the requirement for internal "umbilical" cables which burden mechanical limitations, decrease the reliability and complicate manufacturing and service.

摘要翻译： SCSI适配器卡，提供一个或多个内部SCSI通道，并包括提供外部SCSI连接器的可选子卡的连接器。 子卡是并行夹层式子板，提供模块化和可升级的SCSI总线路由选项。 在优选实施例中，适配器卡包括提供两个内部SCSI信道的两个SCSI控制器。 子板最多可包含2个SCSI控制器，用于附加SCSI通道。 子板可以根据各种SCSI路由选项将一个或多个内部SCSI通道重新路由到外部连接器，或者可以包括用于其他SCSI通道的一个或多个SCSI控制器。 在一个实施例中，子板不包括SCSI控制器，而是用于将一个或多个内部SCSI控制器重新路由到外部连接器。 在第二实施例中，子板包括除了内部SCSI信道之外提供外部SCSI信道的一个或多个SCSI控制器。 将外部SCSI连接器并入子板上消除了基本PWA附加卡以包含外部SCSI连接器的需要，并且还消除了对内部“脐带”电缆的需求，这些电缆会增加机械限制，降低可靠性并使制造复杂化 和服务。

公开(公告)号：US20090121756A1

公开(公告)日：2009-05-14

申请号：US12294010

申请日：2007-03-20

申请人： Manoj Chandran ,  Jay Lory

发明人： Manoj Chandran ,  Jay Lory

IPC分类号： H03L7/00

CPC分类号： H04L7/0012 ,  G11C19/00

摘要： Methods and apparatus for implementing and operating one or more pseudo-synchronous registers with reduced power consumption, and reduced complexity for transferring data between clock domains. Various embodiments of the present invention replace conventional continuous clocking schemes with a strobe signal that is only generated when a data transfer operation with the one or more pseudo-synchronous registers is to take place. The strobe signal is generated so as to have a duration of one full cycle of the clock signal which defines the clock domain in which the at least one pseudo-synchronous register resides.

摘要翻译： 用于实现和操作具有降低的功耗的一个或多个伪同步寄存器的方法和装置，以及降低在时钟域之间传送数据的复杂性。 本发明的各种实施例用仅在要发生与一个或多个伪同步寄存器的数据传送操作时产生的选通信号来代替常规的连续计时方案。 产生选通信号以便具有定义至少一个伪同步寄存器所在的时钟域的时钟信号的一整个周期的持续时间。

公开(公告)号：US5729767A

公开(公告)日：1998-03-17

申请号：US319689

申请日：1994-10-07

申请人： Craig S. Jones ,  Victor K. Pecone ,  Jay Lory

发明人： Craig S. Jones ,  Victor K. Pecone ,  Jay Lory

IPC分类号： G06F11/00 ,  G06F11/20 ,  G06F11/22 ,  G06F11/267 ,  G06F11/34 ,  G06F13/00

CPC分类号： G06F11/1433 ,  G06F11/073 ,  G06F11/0745 ,  G06F11/0781 ,  G06F11/22 ,  G06F11/2236 ,  G06F11/006 ,  G06F11/2205 ,  G06F11/3476

摘要： A computer system including a host CPU, a primary PCI bus coupled to the CPU, and a bus adapter coupled to the primary PCI bus, wherein the host CPU can access peripherals comprised in the bus adapter even when the bus adapter is inoperable. The bus adapter includes a PCI to PCI interface controller which includes a primary PCI interface for coupling to the primary PCI bus and a secondary PCI interface bridge for coupling to a secondary PCI bus. Peripheral bus interface logic is coupled between the primary PCI interface and the secondary PCI interface, and this interface logic couples to various peripheral devices, including ROM/Flash memory and non-volatile static random access memory (NVSRAM). According to the present invention, a host utility executing on the CPU can access the peripheral devices without having to access the secondary PCI bus. Thus, if the secondary PCI bus becomes inoperable or the local processor is unable to boot, the host can still access the memory in the peripheral devices because the peripheral interface is effectively decoupled from the secondary PCI bus and the local processor. The present invention includes a host utility which can update the Flash memory, thereby providing a cost-effective and efficient mechanism for restoring code in a corrupted Flash device on a failed board. This also enables the Flash memory to be programmed for the first time during manufacturing. The system and method of the present invention allows the host CPU to access the NVRAM to obtain event failure information even if the secondary PCI bus has failed.

摘要翻译： 包括主机CPU，耦合到CPU的主PCI总线和耦合到主PCI总线的总线适配器的计算机系统，其中即使总线适配器不可操作，主机CPU也可以访问包含在总线适配器中的外围设备。 总线适配器包括PCI至PCI接口控制器，其包括用于耦合到主PCI总线的主PCI接口和用于耦合到辅助PCI总线的辅助PCI接口桥。 外部总线接口逻辑耦合在主PCI接口和辅助PCI接口之间，并且该接口逻辑耦合到各种外围设备，包括ROM /闪存和非易失性静态随机存取存储器（NVSRAM）。 根据本发明，在CPU上执行的主机实用程序可以访问外围设备，而不必访问辅助PCI总线。 因此，如果辅助PCI总线变得不可操作或本地处理器无法引导，则主机仍然可以访问外围设备中的存储器，因为外围接口有效地与辅助PCI总线和本地处理器分离。 本发明包括可以更新闪存的主机实用程序，从而提供用于在故障板上的损坏的闪存设备中恢复代码的成本有效且有效的机制。 这也使得在制造过程中首次对闪存进行编程。 本发明的系统和方法允许主机CPU访问NVRAM以获得事件故障信息，即使辅助PCI总线发生故障。

公开(公告)号：US5619728A

公开(公告)日：1997-04-08

申请号：US326570

申请日：1994-10-20

申请人： Craig S. Jones ,  Jay Lory ,  Victor K. Pecone

发明人： Craig S. Jones ,  Jay Lory ,  Victor K. Pecone

IPC分类号： G06F13/28 ,  H01J3/00

CPC分类号： G06F13/28

摘要： A peripheral resource controller such as a caching disk array controller is provided for controlling the transfer of data between a host bus and a peripheral resource, such as an array of hard disk drives. The peripheral resource controller includes a bus interface controller for providing an interface between the host bus and a local bus of the peripheral controller. The bus interface controller further includes a peripheral bus interface which accommodates accesses to a peripheral bus and a DMA controller for controlling direct memory access operations between a local memory of the peripheral controller and a system memory of the host computer. A DMA transfer list memory is coupled to the peripheral bus for storing DMA transfer information. The DMA controller fetches host and local address as well as block size information from the DMA transfer list memory to thereby effectuate DMA operations. In one specific implementation, a local processor of the peripheral controller loads the DMA transfer information into the DMA transfer list memory by causing the execution of one or more memory write cycles on the local bus. A local bus interface of the bus interface controller responds as a target and routes the data to a peripheral bus interface. The peripheral bus interface, which functions as a master of the peripheral bus, responsively effectuates corresponding cycles on the peripheral bus to write the DMA transfer information into the DMA transfer list memory.

摘要翻译： 提供诸如缓存磁盘阵列控制器之类的外围资源控制器，用于控制主机总线与诸如硬盘驱动器阵列的外围资源之间的数据传输。 外围资源控制器包括总线接口控制器，用于在主机总线和外围控制器的本地总线之间提供接口。 总线接口控制器还包括外围总线接口，其适应对外围总线的访问和用于控制外围控制器的本地存储器与主计算机的系统存储器之间的直接存储器访问操作的DMA控制器。 DMA传输列表存储器耦合到外围总线以存储DMA传输信息。 DMA控制器从DMA传输列表存储器中获取主机和本地地址以及块大小信息，从而实现DMA操作。 在一个具体实现中，外围控制器的本地处理器通过在本地总线上执行一个或多个存储器写周期来将DMA传输信息加载到DMA传输列表存储器中。 总线接口控制器的本地总线接口作为目标进行响应，并将数据路由到外设总线接口。 用作外设总线主机的外设总线接口响应于外设总线上的相应周期，将DMA传输信息写入DMA传输列表存储器。

公开(公告)号：US5911084A

公开(公告)日：1999-06-08

申请号：US24719

申请日：1998-02-17

申请人： Craig S. Jones ,  Victor K. Pecone ,  Jay Lory

发明人： Craig S. Jones ,  Victor K. Pecone ,  Jay Lory

IPC分类号： G06F11/00 ,  G06F11/20 ,  G06F11/22 ,  G06F11/267 ,  G06F11/34 ,  G06F13/00

CPC分类号： G06F11/1433 ,  G06F11/073 ,  G06F11/0745 ,  G06F11/0781 ,  G06F11/22 ,  G06F11/2236 ,  G06F11/006 ,  G06F11/2205 ,  G06F11/3476

摘要： A computer system including a host CPU, a primary PCI bus coupled to the CPU, and a bus adapter coupled to the primary PCI bus, wherein the host CPU can access peripherals comprised in the bus adapter even when the bus adapter is inoperable. The bus adapter includes a PCI to PCI interface controller which includes a primary PCI interface for coupling to the primary PCI bus and a secondary PCI interface bridge for coupling to a secondary PCI bus. Peripheral bus interface logic is coupled between the primary PCI interface and the secondary PCI interface, and this interface logic couples to various peripheral devices, including ROM/Flash memory and non-volatile static random access memory (NVSRAM). According to the present invention, a host utility executing on the CPU can access the peripheral devices without having to access the secondary PCI bus. Thus, if the secondary PCI bus becomes inoperable or the local processor is unable to boot the host can still access the memory in the peripheral devices because the peripheral interface is effectively decoupled from the secondary PCI bus and the local processor. The present invention includes a host utility which can update the Flash memory, thereby providing a cost-effective and efficient mechanism for restoring code in a corrupted Flash device on a failed board. This also enables the Flash memory to be programmed for the first time during manufacturing. The system and method of the present invention allows the host CPU to access the NVRAM to obtain event failure information even if the secondary PCI bus has failed.

摘要翻译： 包括主机CPU，耦合到CPU的主PCI总线和耦合到主PCI总线的总线适配器的计算机系统，其中即使总线适配器不可操作，主机CPU也可以访问包含在总线适配器中的外围设备。 总线适配器包括PCI至PCI接口控制器，其包括用于耦合到主PCI总线的主PCI接口和用于耦合到辅助PCI总线的辅助PCI接口桥。 外部总线接口逻辑耦合在主PCI接口和辅助PCI接口之间，并且该接口逻辑耦合到各种外围设备，包括ROM /闪存和非易失性静态随机存取存储器（NVSRAM）。 根据本发明，在CPU上执行的主机实用程序可以访问外围设备，而不必访问辅助PCI总线。 因此，如果辅助PCI总线变得不可操作或本地处理器无法引导，则主机仍然可以访问外围设备中的存储器，因为外围接口有效地从辅助PCI总线和本地处理器分离。 本发明包括可以更新闪存的主机实用程序，从而提供用于在故障板上的损坏的闪存设备中恢复代码的成本有效且有效的机制。 这也使得在制造过程中首次对闪存进行编程。 本发明的系统和方法允许主机CPU访问NVRAM以获得事件故障信息，即使辅助PCI总线发生故障。

公开(公告)号：US5745795A

公开(公告)日：1998-04-28

申请号：US743091

申请日：1996-11-04

申请人： Victor Pecone ,  Jay Lory

发明人： Victor Pecone ,  Jay Lory

IPC分类号： G06F13/40 ,  G06F13/00

CPC分类号： G06F13/409 ,  G06F13/4022

摘要： A SCSI controller card which includes a standard SCSI connector that can support either one or two SCSI channels, as desired. The connector can receive either a standard single channel cable or a specially designed dual channel "Y" cable to provide either one or two SCSI channels, respectively. The SCSI controller card includes logic that determines which cable is installed and switching logic which routes one or two SCSI channels to the connector accordingly. In the preferred embodiment, the SCSI adapter card includes two SCSI controllers which provide two SCSI channels. A first channel is connected directly to pins on the SCSI connector. A second channel is connected to switching logic, and a plurality of ground signals are also connected to the switching logic. The second channel is switched into the SCSI connector if the dual channel "Y" cable is attached to the connector, and the ground signals are switched into the SCSI connector if the "Y" cable is not detected. The SCSI adapter card continuously auto-senses which cable is installed at power-up, i.e., whether the dual channel "Y" cable is installed or a standard single channel cable is installed, and switches in either the second channel or ground signals accordingly. Thus the present invention provides increased connectivity from a single connector as well as modular and upgradable SCSI bus routing options. The single external SCSI connector is mechanically compliant with the SCSI standard, but allows external routing of either one or two SCSI channels.

摘要翻译： SCSI控制器卡，包括可以根据需要支持一个或两个SCSI通道的标准SCSI连接器。 连接器可以接收标准单通道电缆或专门设计的双通道“Y”电缆，分别提供一个或两个SCSI通道。 SCSI控制器卡包括确定安装了哪个电缆的逻辑和相应地将一个或两个SCSI通道路由到连接器的交换逻辑。 在优选实施例中，SCSI适配器卡包括提供两个SCSI信道的两个SCSI控制器。 第一个通道直接连接到SCSI连接器上的引脚。 第二通道连接到开关逻辑，并且多个接地信号也连接到开关逻辑。 如果没有检测到“Y”电缆，如果双通道“Y”电缆连接到连接器，则第二个通道切换到SCSI连接器，并将接地信号切换到SCSI连接器。 SCSI适配器卡连续自动检测上电时安装的电缆，即是否安装双通道“Y”电缆，或安装标准单通道电缆，并相应地切换第二通道或接地信号。 因此，本发明提供来自单个连接器的增加的连接以及模块化和可升级的SCSI总线路由选项。 单个外部SCSI连接器符合SCSI标准，但允许外部路由一个或两个SCSI通道。