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1.发明授权ATM cell scheduler which uses a heap memory and associates timestamps with each channel 失效ATM信元调度器，它使用堆存储器并将时间戳与每个信道相关联公开(公告)号：US06205151B1
公开(公告)日：2001-03-20
申请号：US08993801
申请日：1997-12-18
申请人： Jeffrey R. Quay , Brian J. Karguth , Sharat Prasad
发明人： Jeffrey R. Quay , Brian J. Karguth , Sharat Prasad
IPC分类号： H04L1228
CPC分类号： H04L12/5602 , H04L2012/5679 , H04Q11/0478
摘要： A network hub and Asynchronous Transfer Mode (ATM) translator system (5) for use in a Local Area Network (LAN)-based communications system is disclosed. The network hub and ATM translator system (5) includes a host controller (10) that serves as the LAN hub, and which interfaces with a translator card (15) which includes a segmentation and reassembly device (12) in connection with SONET receive/transmit circuitry (20) that communicates with a transceiver (22) to transmit and receive ATM packet cells over a communications facility (FO). The translator card (15) also includes a scheduler (14) that includes a heap sort state machine (36) which maintains a sorted list of entries, in a heap fashion, in on-chip parameter memory (44) and off-chip parameter memory (18). The entries include, for each ATM channel, a channel identifier and a timestamp that indicates the time at which the next cell for the channel will be due for transmission. A due comparator (40) compares the timestamp of the root value in the heap (i.e., the channel with the next due cell) to a global time generated by a reference timer (38), and indicates to a source behavior processor (24) in the scheduler (14) that a cell is due for transmission. The scheduler than issues a transmit credit for the cell, and communicates this event with the SAR device (12) to effect the transmission as appropriate.
摘要翻译： 公开了一种用于基于局域网（LAN）的通信系统中的网络集线器和异步传输模式（ATM）转换器系统（5）。 网络集线器和ATM转换器系统（5）包括用作LAN集线器的主机控制器（10），并且与转换器卡（15）进行接口，转换器卡（15）包括与SONET接收/接收装置相关联的分段和重组装置（12） 发送电路（20），其与收发器（22）通信以通过通信设施（FO）发送和接收ATM分组信元。 翻译卡（15）还包括调度器（14），其包括堆排序状态机（36），其以堆的方式在片上参数存储器（44）中维护条目的排序列表，并且片外参数 记忆（18）。 对于每个ATM信道，这些条目包括指示信道的下一个小区将被传送到何时间的信道标识符和时间戳。 适当的比较器（40）将堆中的根值（即，通道与下一个适当单元）的时间戳与参考定时器（38）生成的全局时间进行比较，并向源行为处理器（24）指示， 在调度器（14）中，单元将要传输。 调度器比发送小区的发送信用，并将该事件与SAR设备（12）进行通信，以适当地进行传输。
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2.发明授权
公开(公告)号：US6115360A
公开(公告)日：2000-09-05
申请号：US994332
申请日：1997-12-19
申请人： Jeffrey R. Quay , Brian J. Karguth
发明人： Jeffrey R. Quay , Brian J. Karguth
CPC分类号： H04L12/5602 , H04Q11/0478 , H04L2012/5616 , H04L2012/5651 , H04L2012/5679
摘要： A network hub and Asynchronous Transfer Mode (ATM) translator system (5) for use in a Local Area Network (LAN)-based communications system is disclosed. The network hub and ATM translator system (5) includes a host controller (10) that serves as the LAN hub, and which interfaces with a translator card (15) which includes a segmentation and reassembly device (12) in connection with SONET receive/transmit circuitry (20) that communicates with a transceiver (22) to transmit and receive ATM packet cells over a communications facility (FO). The translator card (15) also includes a scheduler (14) that includes a heap sort state machine (36) which maintains a sorted list of entries, in a heap fashion, in on-chip parameter memory (44) and off-chip parameter memory (18). The entries include, for each ATM channel, a channel identifier and a timestamp that indicates the time at which the next cell for the channel will be due for transmission. A due comparator (40) compares the timestamp of the root value in the heap (i.e., the channel with the next due cell) to a global time generated by a reference timer (38), and indicates to a source behavior processor (24) in the scheduler (14) that a cell is due for transmission. The scheduler than issues a transmit credit for the cell, and communicates this event with the SAR device (12) to effect the transmission as appropriate.
摘要翻译： 公开了一种用于基于局域网（LAN）的通信系统中的网络集线器和异步传输模式（ATM）转换器系统（5）。 网络集线器和ATM转换器系统（5）包括用作LAN集线器的主机控制器（10），并且与转换器卡（15）进行接口，转换器卡（15）包括与SONET接收/接收装置相关联的分段和重组装置（12） 发送电路（20），其与收发器（22）通信以通过通信设施（FO）发送和接收ATM分组信元。 翻译卡（15）还包括调度器（14），其包括堆排序状态机（36），其以堆的方式在片上参数存储器（44）中维护条目的排序列表，并且片外参数 记忆（18）。 对于每个ATM信道，这些条目包括指示信道的下一个小区将被传送到何时间的信道标识符和时间戳。 适当的比较器（40）将堆中的根值（即，通道与下一个适当单元）的时间戳与参考定时器（38）生成的全局时间进行比较，并向源行为处理器（24）指示， 在调度器（14）中，单元将要传输。 调度器比发送小区的发送信用，并将该事件与SAR设备（12）进行通信，以适当地进行传输。
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公开(公告)号：US08926733B2
公开(公告)日：2015-01-06
申请号：US13696643
申请日：2011-05-13
CPC分类号： B01D67/003 , B01D71/64 , B01D2323/18 , B01D2323/24 , C08L77/00 , C08L79/04 , C08L79/08
摘要： A method for preparing a polymeric material includes: providing a polymeric matrix having at least one polymer and at least one porogen; and degrading the at least one porogen at a temperature T≦1.1 Tg, where Tg is a glass transition temperature of the polymeric matrix. The degrading step includes exposing the polymeric matrix to thermal degradation, chemical degradation, electrical degradation and/or radiation degradation, wherein the polymeric material has a permeability at least 1.2 times a permeability of the polymeric matrix for a gas, and a selectivity of the polymeric material is at least 0.35 times a selectivity of the polymeric matrix for a gas pair. The method preferably provides gas separation membranes that exceed Robeson's upper bound relationship for at least one gas separation pair. Novel polymeric materials, gas separation membranes and fluid component separation methods are also described.
摘要翻译： 制备聚合材料的方法包括：提供具有至少一种聚合物和至少一种致孔剂的聚合物基质; 并在温度T＆lt; IlE下降解至少一种致孔剂; 1.1 Tg，其中Tg是聚合物基质的玻璃化转变温度。 降解步骤包括将聚合物基质暴露于热降解，化学降解，电降解和/或辐射降解，其中聚合物材料具有至少1.2倍的聚合物基质对于气体的渗透性，并且聚合物的选择性 材料是气体对的聚合物基质的选择性的至少0.35倍。 该方法优选提供超过用于至少一个气体分离对的Robeson上限关系的气体分离膜。 还描述了新颖的聚合物材料，气体分离膜和流体组分分离方法。
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4.发明授权High performance polyurethane coating compositions and processes for making same 失效高性能聚氨酯涂料组合物及其制备方法
公开(公告)号：US5115071A
公开(公告)日：1992-05-19
申请号：US682790
申请日：1991-04-09
IPC分类号： C08G18/10 , C08G18/12 , C08G18/48 , C08G18/66 , C09D175/04 , C09D175/06 , C09D175/08
CPC分类号： C09D175/04 , C08G18/10 , C08G18/12 , C08G18/4812 , C08G18/6611
摘要： This invention relates to polyurethane coatings formed from prepolymers made by reacting polyisocyanates with long chain polyols having an average functionality of greater than 2. The resulting prepolymers have equivalent weights greater than about 250 grams per equivalent and preferably greater than about 350 grams per equivalent. An excess of polyisocyanate is reacted with the polyol component at an equivalent ratio of greater than 4:1 equivalents isocyanate per equivalent of polyol. Excess polyisocyanate is then removed from the prepolymer.The resulting polyurethane prepolymers are chain extended with compounds having active hydrogen atoms such as water, amines or short chain polyhydroxy compounds, e.g., diols to form the resulting coatings.
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公开(公告)号：US20130047844A1
公开(公告)日：2013-02-28
申请号：US13696643
申请日：2010-05-13
CPC分类号： B01D67/003 , B01D71/64 , B01D2323/18 , B01D2323/24 , C08L77/00 , C08L79/04 , C08L79/08
摘要： A method for preparing a polymeric material includes: providing a polymeric matrix having at least one polymer and at least one porogen; and degrading the at least one porogen at a temperature T≦1.1 Tg, where Tg is a glass transition temperature of the polymeric matrix. The degrading step includes exposing the polymeric matrix to thermal degradation, chemical degradation, electrical degradation and/or radiation degradation, wherein the polymeric material has a permeability at least 1.2 times a permeability of the polymeric matrix for a gas, and a selectivity of the polymeric material is at least 0.35 times a selectivity of the polymeric matrix for a gas pair. The method preferably provides gas separation membranes that exceed Robeson's upper bound relationship for at least one gas separation pair. Novel polymeric materials, gas separation membranes and fluid component separation methods are also described.
摘要翻译： 制备聚合材料的方法包括：提供具有至少一种聚合物和至少一种致孔剂的聚合物基质; 并在温度T n1E下降解至少一种致孔剂; 1.1 Tg，其中Tg是聚合物基质的玻璃化转变温度。 降解步骤包括将聚合物基质暴露于热降解，化学降解，电降解和/或辐射降解，其中聚合物材料具有至少1.2倍的聚合物基质对于气体的渗透性，并且聚合物的选择性 材料是气体对的聚合物基质的选择性的至少0.35倍。 该方法优选提供超过用于至少一个气体分离对的Robeson上限关系的气体分离膜。 还描述了新颖的聚合物材料，气体分离膜和流体组分分离方法。
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公开(公告)号：US5175230A
公开(公告)日：1992-12-29
申请号：US859210
申请日：1992-03-27
IPC分类号： C08G18/75
CPC分类号： C08G18/758
摘要： This invention pertains to alkyl substituted difunctional cyclohexylisocyanates having an isomer distribution. The isocyanates are represented by the formulas: ##STR1## wherein; R.sup.1 is C.sub.1-4 alkyl; R.sup.2 is C.sub.1-4 alkyl andn is 0 or 2.The invention also relates to polyurethane and polyurethane/urea resins prepared using the alkyl substituted difunctional cyclohexylisocyanates as at least a portion of the polyisocyanate used in forming the polyurethane.
摘要翻译： 本发明涉及具有异构体分布的烷基取代的二官能环己基异氰酸酯。 异氰酸酯由下式表示：其中： R1是C1-4烷基; R2是C1-4烷基，n是0或2.本发明还涉及使用烷基取代的二官能环己基异氰酸酯作为用于形成聚氨酯的多异氰酸酯的至少一部分制备的聚氨酯和聚氨酯/脲树脂。
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7.发明授权Process for the preparation of cyclohexanediisocyanate containing polyisocyanate prepolymers and polyurethanes having high temperature performance 失效制备环己烷二异氰酸酯的多异氰酸酯预聚物和具有高温性能的聚氨酯的方法
公开(公告)号：US4892920A
公开(公告)日：1990-01-09
申请号：US274539
申请日：1988-11-21
申请人： Jeffrey R. Quay , Jeremiah P. Casey
发明人： Jeffrey R. Quay , Jeremiah P. Casey
CPC分类号： C08G18/751 , C08G18/10
摘要： This invention relates to a polyisocyanate prepolymer for polyurethane and polyurethane/urea elastomer synthesis and to the resulting elastomer. The prepolymer is formed by reacting a cyclohexanediisocyanate with a long chain polyol under conditions such that essentially a 2:1 adduct is formed. Excess cyclohexanediisocyanate is removed prior to forming the elastomer.
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8.发明授权Direct memory access controller with split channel transfer capability and FIFO buffering 有权直接存储器访问控制器，具有分离的信道传输能力和FIFO缓冲公开(公告)号：US06311234B1
公开(公告)日：2001-10-30
申请号：US09633998
申请日：2000-08-08
IPC分类号： G06F1328
CPC分类号： G06F9/3001 , G06F9/30098 , G06F15/7832
摘要： A microprocessor 1 is described which includes a direct memory access (DMA) circuitry 143. DMA 143 is interconnected with a program memory 23 and a data memory 22 and is operational to transfer data to or from these memories. DMA 143 is interconnected with a peripheral bus 110 and thereby to various peripherals internal to microprocessor 1. DMA 143 is also interconnected with an external memory interface 103 and thereby to various external memory circuits and peripherals external to microprocessor 1. An auxiliary channel control circuitry 160 provides DMA transfers by interacting with a peripheral such as host port 150 which has its own address generation circuitry. DMA 143 provides frame synchronization for triggering a frame transfer, or group of transfers. DMA 143 is auto-initialized through registers. DMA action complete pins DMAC0-3 indicate DMA status to external devices. DMA 143 allows for local variability of transfer rates in a split channel mode of operation by allowing a transmit channel to get ahead of a corresponding receive channel by a preselected number of data words.
摘要翻译： 描述了包括直接存储器访问（DMA）电路143的微处理器1.DMA 143与程序存储器23和数据存储器22互连，并且可操作以将数据传送到这些存储器或从这些存储器传送数据。 DMA 143与外围总线110互连，从而与微处理器1内部的各种外围设备互连.DMA 143也与外部存储器接口103互连，从而连接到微处理器1外部的各种外部存储器电路和外围设备。辅助通道控制电路160 通过与诸如具有其自己的地址产生电路的主机端口150的外围设备交互来提供DMA传输。 DMA 143提供用于触发帧传送或传送组的帧同步。 DMA 143通过寄存器自动初始化。 DMA操作完成引脚DMAC0-3指示外部设备的DMA状态。 DMA 143允许通过允许发送信道通过预选数量的数据字而在对应的接收信道之前的分离信道操作模式中的传输速率的局部变化。
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9.发明授权DMA controller with split channel transfer capability and FIFO buffering allowing transmit channel to get ahead of corresponding receive channel by preselected number of elements 失效具有分离信道传输能力的DMA控制器和FIFO缓冲，允许发射信道通过预先选择的元素数量超前于相应的接收信道
公开(公告)号：US6145027A
公开(公告)日：2000-11-07
申请号：US54833
申请日：1998-04-03
CPC分类号： G06F9/3001 , G06F15/7832 , G06F9/30098
摘要： A microprocessor 1 is described which includes a direct memory access (DMA) circuitry 143. DMA 143 is interconnected with a program memory 23 and a data memory 22 and is operational to transfer data to or from these memories. DMA 143 is interconnected with a peripheral bus 110 and thereby to various peripherals internal to microprocessor 1. DMA 143 is also interconnected with an external memory interface 103 and thereby to various external memory circuits and peripherals external to microprocessor 1. An auxiliary channel control circuitry 160 provides DMA transfers by interacting with a peripheral such as host port 150 which has its own address generation circuitry. DMA 143 provides frame synchronization for triggering a frame transfer, or group of transfers. DMA 143 is auto-initialized through registers. DMA action complete pins DMAC0-3 indicate DMA status to external devices. DMA 143 allows for local variability of transfer rates in a split channel mode of operation by allowing a transmit channel to get ahead of a corresponding receive channel by a preselected number of data words.
摘要翻译： 描述了包括直接存储器访问（DMA）电路143的微处理器1.DMA 143与程序存储器23和数据存储器22互连，并且可操作以将数据传送到这些存储器或从这些存储器传送数据。 DMA 143与外围总线110互连，从而与微处理器1内部的各种外围设备互连.DMA 143也与外部存储器接口103互连，从而连接到微处理器1外部的各种外部存储器电路和外围设备。辅助通道控制电路160 通过与诸如具有其自己的地址产生电路的主机端口150的外围设备交互来提供DMA传输。 DMA 143提供用于触发帧传送或传送组的帧同步。 DMA 143通过寄存器自动初始化。 DMA操作完成引脚DMAC0-3指示外部设备的DMA状态。 DMA 143允许通过允许发送信道通过预选数量的数据字而在对应的接收信道之前的分离信道操作模式中的传输速率的局部变化。
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