公开(公告)号：US6103555A

公开(公告)日：2000-08-15

申请号：US661188

申请日：1996-06-10

申请人： Jeong Yeol Choi

发明人： Jeong Yeol Choi

IPC分类号： H01L23/525 ,  H01L21/82

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10S438/956

摘要： The reliability of an antifuse can be increased and/or the thickness of the antifuse dielectric can be decreased by the use of a rapid thermal nitridation nitride layer as part of the antifuse dielectric. The RTN nitride layer is denser and has fewer pinholes than nitride layers formed by chemical vapor deposition. The rapid thermal nitridation also produces a good contact with a bottom electrode containing silicon as well as providing a nucleation layer for any additional nitride layer formed by chemical vapor deposition. Increasing the reliability of the antifuse dielectric allows it to be thinner, and thus allows for the programming of the dielectric layer at lower programming voltages.

摘要翻译： 通过使用快速氮化氮化物层作为反熔丝电介质的一部分，可以提高反熔丝的可靠性和/或可以降低反熔丝电介质的厚度。 RTN氮化物层比通过化学气相沉积形成的氮化物层更致密且具有更少的针孔。 快速热氮化还与含硅的底部电极产生良好的接触，以及为通过化学气相沉积形成的任何另外的氮化物层提供成核层。 提高反熔丝电介质的可靠性允许其更薄，从而允许在较低编程电压下编程电介质层。

公开(公告)号：US6063676A

公开(公告)日：2000-05-16

申请号：US871139

申请日：1997-06-09

申请人： Jeong Yeol Choi ,  Chung-Chyung Han ,  Ken-Chuen Mui

发明人： Jeong Yeol Choi ,  Chung-Chyung Han ,  Ken-Chuen Mui

IPC分类号： H01L21/225 ,  H01L21/336 ,  H01L21/768

CPC分类号： H01L29/6659 ,  H01L21/76895 ,  H01L29/41783 ,  H01L21/2257

摘要： A semiconductor substrate having a surface, a field oxide region at the surface and a gate structure above the surface are provided. A sidewall spacer is formed adjacent to the gate structure and a polysilicon layer is formed above the substrate, the polysilicon layer having raised first and second portions above the gate structure and field oxide region, respectively. A masking layer is formed above the polysilicon layer and then blanket etched to expose the raised first and second portions of the polysilicon layer which are subsequently removed to form a raised source/drain region from the polysilicon layer. Since the raised source/drain region is fabricated without using photolithography, high density MOSFETs are readily fabricated.

摘要翻译： 提供具有表面的表面，表面处的场氧化物区域和表面上方的栅极结构的半导体衬底。 在栅极结构附近形成侧壁间隔物，并且在衬底上形成多晶硅层，多晶硅层分别在栅极结构和场氧化物区域上方升高第一和第二部分。 掩模层形成在多晶硅层之上，然后被毯式蚀刻以暴露多晶硅层的凸出的第一和第二部分，随后被去除以从多晶硅层形成升高的源极/漏极区。 由于在不使用光刻的情况下制造升高的源极/漏极区域，所以容易制造高密度MOSFET。

公开(公告)号：US6043129A

公开(公告)日：2000-03-28

申请号：US876540

申请日：1997-06-09

申请人： Jeong Yeol Choi ,  Chung-Chyung Han ,  Ken-Chuen Mui

发明人： Jeong Yeol Choi ,  Chung-Chyung Han ,  Ken-Chuen Mui

IPC分类号： H01L21/225 ,  H01L21/285 ,  H01L21/336 ,  H01L21/768 ,  H01L27/088

CPC分类号： H01L29/6659 ,  H01L21/28525 ,  H01L21/76895 ,  H01L27/088 ,  H01L29/41783 ,  H01L21/2257

摘要： A semiconductor substrate having a surface, a planarized field oxide region at the surface and a gate structure overlying the surface are provided. A sidewall spacer is formed adjacent to the gate structure and a polysilicon layer is formed overlying the substrate, the polysilicon layer having a raised first portion overlying the gate structure. A masking layer is formed overlying the polysilicon layer and then blanket etched to expose the raised first portion of the polysilicon layer which is subsequently removed. Since the raised first portion of the polysilicon layer is removed without using photolithography, high density MOSFETs are readily fabricated.

摘要翻译： 提供具有表面，表面处的平坦化场氧化物区域和覆盖表面的栅极结构的半导体衬底。 在栅极结构附近形成侧壁间隔物，并且在衬底上形成多晶硅层，多晶硅层具有覆盖栅极结构的凸起的第一部分。 形成覆盖多晶硅层的掩模层，然后被毯式蚀刻以暴露随后除去的多晶硅层的凸出的第一部分。 由于在不使用光刻的情况下去除多晶硅层的隆起的第一部分，因此容易制造高密度MOSFET。

公开(公告)号：US20090108545A1

公开(公告)日：2009-04-30

申请号：US12091743

申请日：2006-10-26

申请人： Oh-Jin Kwon ,  Jeong-Yong Bae ,  Jeong-Yeol Choi

发明人： Oh-Jin Kwon ,  Jeong-Yong Bae ,  Jeong-Yeol Choi

IPC分类号： B23B31/12

CPC分类号： H01L21/6708 ,  H01L21/68728 ,  Y10T279/18

摘要： The present invention is directed to a spin chuck for use in a process, such as a cleaning process and an etching process, performed while rotating a substrate. The spin chuck includes a spin head on which a substrate is placed, a driving part configured to rotate the spin head, and a fix bracket installed on the spin head and having a contact surface that is in contact with a flat surface of a flat zone of the substrate at a position corresponding to the flat zone to prevent a vortex caused by the flat zone. Since the fix bracket has the same shape as the flat zone of the substrate, an air current unbalance resulting from the flat zone is suppressed to uniformly inject etchants to a rear surface of the substrate.

摘要翻译： 本发明涉及一种旋转卡盘，用于在旋转基板的同时执行诸如清洁处理和蚀刻工艺的工艺。 旋转卡盘包括其上放置基板的旋转头，构造成旋转旋转头的驱动部分和安装在旋转头上的固定支架，并且具有与平坦区域的平坦表面接触的接触表面 在对应于平坦区域的位置处的基板，以防止由平坦区域引起的涡流。 由于固定支架具有与基板的平坦区域相同的形状，所以抑制了从平坦区域产生的气流不平衡，以均匀地将蚀刻剂注入基板的后表面。

公开(公告)号：US20060037499A1

公开(公告)日：2006-02-23

申请号：US11135398

申请日：2005-05-24

申请人： Joo-Jib Park ,  Jeong-Yeol Choi

发明人： Joo-Jib Park ,  Jeong-Yeol Choi

IPC分类号： B41F17/00

CPC分类号： H01L21/68707

摘要： A substrate transport apparatus is provided for stably transporting a substrate and sensing a receiving state of the substrate. The substrate transport apparatus includes a grip member for gripping a substrate placed on the pocket part of the hand when a hand returns to a groove position from a pickup position. The grip member may include a pusher and an elastic member. The pusher has a curved section contacting the edge of a substrate and is mounted on the base to move in the same direction as the at least one hand, and the elastic member supplies an elastic force for enabling the pusher to laterally press the edge of the substrate.

摘要翻译： 提供了用于稳定地输送基板并感测基板的接收状态的基板输送装置。 基板输送装置包括握持构件，用于当手从拾取位置返回到凹槽位置时，夹持放置在手的口袋部分上的基底。 夹持构件可以包括推动器和弹性构件。 推动器具有与基板的边缘接触的弯曲部分，并且安装在基座上以与至少一只手相同的方向移动，并且弹性构件提供弹性力，以使推动器能够横向按压 基质。

公开(公告)号：US06894356B2

公开(公告)日：2005-05-17

申请号：US10099520

申请日：2002-03-15

申请人： Jeong Yeol Choi

发明人： Jeong Yeol Choi

IPC分类号： H01L21/8244 ,  H01L27/105 ,  H01L27/11 ,  H01L29/76

CPC分类号： H01L27/11 ,  H01L27/105 ,  H01L27/1104 ,  H01L27/1116

摘要： A static random access memory (SRAM) cell is given increased stability and latch-up immunity by fabricating the PMOS load transistors of the SRAM cell to have a very low drain/source dopant concentration. The drain/source regions of the PMOS load transistors are formed entirely by a P−− blanket implant. The PMOS load transistors are masked during subsequent implant steps, such that the drain/source regions of the PMOS load transistors do not receive additional P-type (or N-type) dopant. The P−− blanket implant results in PMOS load transistors having drain/source regions with dopant concentrations of 1e17 atoms/cm3 or less. The dopant concentration of the drain/source regions of the PMOS load transistors is significantly lower than the dopant concentration of lightly doped drain/source regions in PMOS transistors used in peripheral circuitry.

摘要翻译： 静态随机存取存储器（SRAM）单元通过制造SRAM单元的PMOS负载晶体管具有非常低的漏极/源极掺杂剂浓度而被提供增加的稳定性和闭锁抗扰度。 PMOS负载晶体管的漏极/源极区域完全由P--覆盖植入物形成。 在随后的注入步骤期间，PMOS负载晶体管被掩蔽，使得PMOS负载晶体管的漏极/源极区域不接收附加的P型（或N型）掺杂剂。 P--覆盖式注入导致具有掺杂剂浓度为1e17原子/ cm 3或更低的漏极/源极区的PMOS负载晶体管。 PMOS负载晶体管的漏极/源极区域的掺杂剂浓度显着低于在外围电路中使用的PMOS晶体管中的轻掺杂漏极/源极区域的掺杂剂浓度。

公开(公告)号：US6165918A

公开(公告)日：2000-12-26

申请号：US306654

申请日：1999-05-06

申请人： James Yingbo Jia ,  Jeong-Yeol Choi

发明人： James Yingbo Jia ,  Jeong-Yeol Choi

IPC分类号： H01L21/8234 ,  H01L21/8238

CPC分类号： H01L21/823462 ,  Y10S438/981

摘要： Systems and methods are described for fabricating semiconductor gate oxides of different thicknesses. Two methods for forming gate oxides of different thicknesses in conjunction with local oxidation of silicon (LOCOS) are disclosed. Similarly, two methods for forming gate oxides of different thicknesses in conjunction with shallow trench isolation (STI) are disclosed. Techniques that use two poly-silicon sub-layers of substantially equal thickness and techniques that use two poly-silicon sub-layers of substantially unequal thickness are described for both LOCOS and STI. The systems and methods provide advantages because gate uniformity and quality are improved, the processes and resulting devices are cleaner, and there is less degradation of carrier mobility.

摘要翻译： 描述了制造不同厚度的半导体栅极氧化物的系统和方法。 公开了两种形成不同厚度的栅氧化物结合局部氧化硅（LOCOS）的方法。 类似地，公开了与浅沟槽隔离（STI）结合形成不同厚度的栅极氧化物的两种方法。 对于LOCOS和STI都描述了使用基本相等厚度的两个多硅子层和使用基本上不等厚度的两个多晶硅子层的技术的技术。 系统和方法提供了优点，因为栅极均匀性和质量得到改善，工艺和所得到的器件更清洁，载体迁移率降低较少。

公开(公告)号：US5830789A

公开(公告)日：1998-11-03

申请号：US751464

申请日：1996-11-19

申请人： Chuen-Der Lien ,  Jeong Yeol Choi

发明人： Chuen-Der Lien ,  Jeong Yeol Choi

IPC分类号： H01L21/8238 ,  H01L27/092

CPC分类号： H01L27/0928 ,  H01L21/823892

摘要： A substrate has defined therein one or more active regions. A layer of polysilicon is deposited and patterned to form gates for various CMOS devices. A masking layer is then deposited and selectively etched to leave exposed portions of the substrate. Dopants of a first conductivity type are implanted into the exposed portions of the substrate to form one or more well regions of the first conductivity type. Using this masking layer and the polysilicon gates left exposed thereby as a mask, dopants of a second conductivity type are then implanted into the substrate to form source and drain regions of the second conductivity type in the well regions of the first conductivity type. The masking layer is then removed. In this manner, source and drain regions may be formed using the same masking layer used to define the well within which the source and drain regions lie, thereby reducing both time and expense in the fabrication of CMOS devices.

摘要翻译： 衬底中限定有一个或多个活性区域。 一层多晶硅沉积并图案化以形成各种CMOS器件的栅极。 然后沉积掩模层并选择性地蚀刻以留下衬底的暴露部分。 将第一导电类型的掺杂剂注入到衬底的暴露部分中以形成第一导电类型的一个或多个阱区域。 使用该掩模层和由此露出的多晶硅栅极作为掩模，然后将第二导电类型的掺杂剂注入到衬底中，以在第一导电类型的阱区中形成第二导电类型的源区和漏区。 然后去除掩模层。 以这种方式，可以使用用于限定源极和漏极区域所在的阱的相同掩模层来形成源极和漏极区域，由此在CMOS器件的制造中减少时间和费用。

公开(公告)号：US07316537B2

公开(公告)日：2008-01-08

申请号：US11135398

申请日：2005-05-24

申请人： Joo-Jib Park ,  Jeong-Yeol Choi

发明人： Joo-Jib Park ,  Jeong-Yeol Choi

IPC分类号： B25J18/04

CPC分类号： H01L21/68707

摘要： A substrate transport apparatus is provided for stably transporting a substrate and sensing a receiving state of the substrate. The substrate transport apparatus includes a grip member for gripping a substrate placed on the pocket part of the hand when a hand returns to a groove position from a pickup position. The grip member may include a pusher and an elastic member. The pusher has a curved section contacting the edge of a substrate and is mounted on the base to move in the same direction as the at least one hand, and the elastic member supplies an elastic force for enabling the pusher to laterally press the edge of the substrate.

摘要翻译： 提供了用于稳定地输送基板并感测基板的接收状态的基板输送装置。 基板输送装置包括握持构件，用于当手从拾取位置返回到凹槽位置时，夹持放置在手的口袋部分上的基底。 夹持构件可以包括推动器和弹性构件。 推动器具有与基板的边缘接触的弯曲部分，并且安装在基座上以与至少一只手相同的方向移动，并且弹性构件提供弹性力，以使推动器能够横向按压 基质。

公开(公告)号：US06496399B1

公开(公告)日：2002-12-17

申请号：US09941372

申请日：2001-08-28

申请人： Jeong Yeol Choi ,  Sang-Yun Lee

发明人： Jeong Yeol Choi ,  Sang-Yun Lee

IPC分类号： G11C1500

CPC分类号： G11C15/04

摘要： A ternary CAM system includes a main memory cell configured to store complementary data signals D/D#. A first transistor has a source coupled to receive data signal D#, and a gate coupled to receive a compare signal C. A second transistor has a source coupled to receive data signal D, and a gate coupled to receive complementary compare signal C#. A third transistor has a gate coupled to drain regions of the first and second transistors. A mask cell storing a mask value is coupled to the source of the third transistor. A pre-charged match line is coupled to the drain of the third transistor. If compare signals C/C# match data signals D/D#, then the third transistor is turned off, thereby isolating match line and mask cell. If compare signals C/C# don't match data signals D/D#, then the third transistor is turned on, thereby coupling mask cell and match line.

摘要翻译： 三元CAM系统包括被配置为存储辅助数据信号D / D＃的主存储单元。 第一晶体管具有耦合以接收数据信号D＃的源极和耦合以接收比较信号C的栅极。第二晶体管具有耦合以接收数据信号D的源极和耦合以接收互补比较信号C＃的栅极。 第三晶体管具有耦合到第一和第二晶体管的漏极区的栅极。 存储掩模值的掩模单元耦合到第三晶体管的源极。 预充电匹配线耦合到第三晶体管的漏极。 如果比较信号C / C＃匹配数据信号D / D＃，则第三晶体管截止，从而隔离匹配线和掩模单元。 如果比较信号C / C＃不匹配数据信号D / D＃，则第三晶体管导通，从而耦合屏蔽单元和匹配线。